New-Tech Europe Magazine | June 2018

Analog Defect Analysis Reduces Test Cost and Reduces Test Escapes In this release, Cadence introduces a simulation engine to enable a new test methodology for analog ICs—defect-oriented testing—that expands the capabilities of test far beyond what is traditionally achieved by just performing functional and parametric tests. Defect-oriented testing allows designers to evaluate the ability to eliminate die with manufacturing defects and resulting test escapes that cause field failures. It can also be used to optimize wafer test, reducing the number of tests required to achieve the target defect coverage by eliminating over- testing and potentially reducing the number of tests up to 30 percent. Customer experience with the tool indicates that it accelerates defect simulation by more than 100X. “Analog defect simulation is becoming very important for us to meet our customers’ expectations,” statedDieter Härle, projectmanager, Infineon Austria. “We tested the Legato Reliability Solution and were able to accelerate the simulation time by a factor of more than 100. We verified the solution and plan to adopt it for use in our production flow.” Electro-Thermal Analysis Prevents Thermal Overstress In this release, Cadence is introducing a dynamic electro- thermal simulation engine. For automotive designers, for example, actual usage results in significant temperature rise during normal operation due to on-chip losses and power dissipated in the switches. In

addition, these components need to operate in hostile environments under the hood of an automobile. The combination of high-power dissipation in a high-temperature environment can result in thermal overstress that can result in failure during normal operation. Dynamic electro-thermal simulation allows designers to simulate the on-chip temperature rise and validate the operation of over temperature protection circuits. Advanced Aging Analysis Predicts Product Wear-out Cadence is the recognized leader in aging analysis, providing technologies like RelXpert and AgeMOS to analyze the device degradation due to electrical stress. In this release, Cadence is enhancing aging analysis to include the effects that accelerate device wear-out including temperature and process variation. Cadence also provides a new aging model

for device degradation in advanced nodes with FinFET transistors. This holistic approach to aging analysis allows designers to achieve their design lifetime targets with less over-design. About Cadence Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. Thecompany’sSystem Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.

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