New-Tech Europe Magazine | April 2019

During development, models can grow much larger as they’re optimized and trained on the full range of inputs that they might see. This means that, over the course of a given project – and particularly when a past project is built on a new project – the verification platform must grow or shrink to accommodate the wide range in resources required over the lifespan of the projects – while minimizing any effect on performance. This drives the need for scalability. Finally, AI algorithms are new; there is no legacy. That means that, even if you wanted to use ICE, there are few sources of real data from older design implementations that could be used to validate a new implementation. This is all new stuff. As a result, we must build a virtual verification environment. Even if we could use ICE, a virtual environment is still preferable. During debug, for example, you can’t stop an ICE source’s clock. You may stop looking at data, but the source keeps moving without you. By contrast, a virtualized data source is virtual in all regards, including the clock. So you can stop a design at a critical point, probe around to see what’s happening, and then continue on from the exact same spot. This helps the determinism that we already saw we need. And so this drives the need for virtualization. Figure 1: Application of AI/ML designs

Figure 2: Virtualization Enables running AI/ML Frameworks under Performance Benchmarks

Veloce Characteristics Thesethreerequirements–determinism, scalability, and virtualization – align perfectly with Veloce emulators’ three key pillars. Verification on Veloce emulators can be completely deterministic. Whether testing hardware or software, you can repeat runs over and over, probing hardware and single-stepping code until every aspect of your design’s behavior has been checked out. Veloce emulators are scalable from 40 million to 15 billion gates. Whatever the size and complexity of your design and models, the Veloce platform is a “right sized” resource for verification. As your design scales up, your emulation platform can scale in capacity without performance compromise to ensure you can complete your verification on schedule. The complete set of information needed for design verification on the Veloce emulator can be virtualized. Whether leveraging any of the many ready-built verification blocks or designing your own, you have full visibility and full freedom to control the execution of the verification suite. This includes debug issues and the precise measurements of important system behavior parameters. In Conclusion Artificial intelligence and ML is forcing us to think in new ways about design

and verification. Veloce emulators, already important for many of the markets into which AI is moving, will be an even more important tool in ensuring that your AI-enabled projects get the verification they critically need in a timeframe that gets you to market on time. Jean-Marie Brunet is the Senior Marketing Director for the Emulation Division at Mentor, a Siemens Business. He has served for over 20 years in application engineering, marketing and management roles in the EDA industry, and has held IC design and design management positions at STMicrolectronics, Cadence, and Micron among others. Jean-Marie holds a Master's degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France.