New-Tech Europe Magazine | Q2 2022

Flash products and is therefore considered a realistic target. To become a viable storage solution for nearline applications, the technology must also have adequate response time, bandwidth (e.g. 20Gb/s), cycling endurance (103 write/read cycles), energy consumption (a few pJ to write a bit), and retention (over 10 years). These evaluations will be the subject of further research, building on imec’s 300mm liquid memory test platforms with both colloidal and electrolithic cells in different configurations. About the author Maarten Rosmeulen Maarten Rosmeulen received his M.Sc. degree in physics in 1993 and the M.Sc. degree in physics of micro-electronics and materials science in 1994, both from the KU Leuven, Belgium. In 2005, he received the Ph.D. degree in electrical engineering from the KU Leuven. Since then, he is with imec, Leuven, Belgium where he has been active as an R&D engineer in process integration, semiconductor device design and electrical device characterization for multiple internal and external projects. In 2009 he became project leader for the development of GaN-on-Silicon Light Emitting Diodes (LEDs). In 2014 he became team leader of the Pixel Design and Testing team and has been responsible for the development of CMOS Image Sensor (CIS) technologies. In 2019 he became program director of the Storage Memory program, the position he holds today.

the second generation of electrolithic memory cells, designed to write and read signals from an extensive array of parallelized nanowells (80 – 150nm diameter, 300nm deep). Preliminary results show that the read signals obtained after dissolving a Cu/CoNi five- layer stack correspond well to the writing (i.e., deposition) operation (see figure 7). Towards industrial adoption: improving density, response time, bandwidth, endurance, and retention These new liquid-based memories are still in an exploratory research stage, with the electrolithic memory being the most advanced. Nevertheless, industry has already shown considerable interest in these concepts. At imec, we envisage their introduction in the memory roadmap from 2030 onwards, when the bit density scaling of 3D-NAND-Flash will start saturating. With further scaling efforts, we anticipate that with these approaches, the bit storage density can be pushed towards the 1Tbit/ mm2 range at a lower process cost per mm2 compared to 3D-NAND-Flash. For liquid memories, such an ultrahigh density can only be achieved if electrodes and capillaries are made on a pitch of 40nm. Also, researchers must be able to make capillaries with aspect ratios of about 400:1 and 165:1 for colloidal and electrolithic memory, respectively. This is similar to the aspect ratios of the memory holes needed for making future 3D-NAND-

of metal B will be alloyed with some amount of A. Reading of the electrolithic memory can be realized by reversing the cell current and monitoring the dissolution potential. In a first proof-of-concept using mm- and µm-sized electrodes, the feasibility of using these techniques for reading and writing could be successful ly demonstrated. For example, for a 4µm diameter electrode, the researchers demonstrated consecutive writing and reading of two layers of CoNi, alternated with three layers of Cu. The experiments also indicated shorter write/read times for µm-sized electrodes than larger ones. Nanometer-sized wells at tight pitches are eventually needed to achieve sufficiently high bit densities and response times. Therefore, the imec researchers fabricated Figure 6. Top view SEM showing microelectrode arrays with electrodes of different sizes in the mm- to µm- range: the first proof of concept (also presented at IMW 2022).

Figure 7. (Left) Second generation of electrolithic memory cells with nanowells and common bottom electrode; (middle) schematic representation of writing the Cu/CoNi 5-layer stack, showing three different writing schemes; (right) read signals, clearly showing the position of the CoNi layer within the stacks. E.g., peaks that appear first in time correspond to the latest deposited CoNi layer.

Maarten Rosmeulen

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