New-TechEurope Magazine | November 2017 | Digital Edition

(shift in frequency), decimation, equalization, and calibration. The resulting narrowband signal then gets demodulated and decoded, further filtered, amplified, and stored to HDD or any combination of these functions. At a high level, typical streaming and channelizing applications can be divided as figure 2 shows. Back to Top Wideband Streaming To better understand the challenges connectedwithwideband streaming, one must first understand the technical specifications of the IF receiver. This paper focuses on the PXIe-5624R module. IF receivers are typically part of the vector signal analyzer that comprises the mixer, IF receiver, and signal sources for LO. The architecture of the example vector signal analyzer is described in the Introduction to the PXIe-5668R—High-Performance 26.5 GHz Wideband Signal Analyzer white paper. IF is characterized by the frequency range from 5 MHz to 2 GHz and bandwidth of 800 MHz typical (see technical specs for details). After adding a band-limited noise (dither) signal, which helps reduce the quantization effects of the ADC and improve spectral performance, the ADC samples the signal at up to 2 GSa/s with 12-bit resolution. The onboard FPGA processes these samples and transfers the data to other devices (PXI Express controller, RAID) through the PCI Express Gen 2x8, which allows for data streaming with theoretical rates of up to 4 GB/s. In the wideband streaming case, the FPGA performs only one digital downconversion (DDC) for all incoming data, as opposed to several independent downconversions in the narrowband case as mentioned later in the document.

Figure 1. Example Signals in 5 MHz–2 GHz Band

Bit Packing When talking about wideband streaming, one must consider not only the theoretical available bandwidth of the PCI Express bus but also its practical limitations (that is, control messages that travel over the same bus). The first and more simple implementation for sending data over the PCI Express bus would be to send 16-bit samples, one after another, even if data from the ADC is only 12 bit. However, this approach leads to theoretical limitations of 4 GB/s per PCI Express link available in the PXIe-5624R module (2 bytes/samples at 2 GS/s equals to

4 GB/s), which practically won’t allow for continuous streaming. However, there’s a clever solution: bit packing. Using bit packing, four 12-bit samples are packed into three 16-bit words. Consequently, this method reduces the data rate from 4 GB/s to 3 GB/s, enabling continuous data streaming. Intermodules Synchronization Often there is a need for continuous streaming from several modules of the same type. These multichannel, synchronized RF systems enable certain applications such as direction finding.

Figure 2. Classification of Streaming Applications Covered in This Document

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