New-Tech Europe | December 2016 | Didital Edition

Comparing CPLD-Based Circuit Board Power Management Architectures

Shyam Chandra, Lattice Semiconductor

Introduction The growing complexity of board- level designs has begun to strain the capabilities of today's hardware/ power management architectures. While any one of the four most commonly used management architectures can be used to support these complex designs, they each require different sets of compromises and design trade-offs in terms of scalability, design effort or cost. Recently, a fifth board management architecture has emerged which provides the best possible performance, safety and flexibility while requiring far less design effort and implementation cost. This article will explore this new architecture, primarily with a focus on the Power Management functions it provides. Overview A circuit board is typically divided into

a disproportionate share of the overall Bill of Materials (BOM) cost. Recently however, a new distributed architecture has been developed which is much more scalable and can be implemented at amuch lower BOM cost. In order to better understand the advantages a distributed architecture offers, we'll look at how Power Management is implemented in four of the most commonly used Hardware Management architectures (illustrated in Figures 2-5) before taking a deep dive into the distributed architecture (illustrated in Figure 7). A comparison of Control PLD based power management architectures In the following analysis, we'll compare how these supplies are managed by each of four commonly used architectures (illustrated in

2 functional blocks (Figure 1), the Payload Management section and the Hardware Management section. In most boards, 80% - 90% of the circuit board is typically devoted to "payload" functionality (data/control plane elements and/or processors). The remaining 10%-20% of board space is occupied by the circuitry which performs hardware-level monitoring/control or housekeeping functions. Unfortunately, most existing Hardware Management solutions have difficulty scaling to address the growing complexity of modern Payload Elements. For example, although the Hardware Management section typically occupies only 10% - 20% of the board, its design/debug effort can consume a much larger percentage the overall development time (30% - 40%). Likewise, the Hardware Manager often consumes

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