New-Tech Europe | December 2016 | Didital Edition

the least board congestion. • The entire system can be implemented in a single design environment (GUI or VHDL/Verilog) • Distributed architecture is highly scalable. • Reduced solution cost because the voltage, current and temperature monitoring functions are integrated within the ASC. • Reduced design time as Power Management and housekeeping functions are together. • Dramatically reduce board debug time using Lattice's standard power debug utilities. Conclusions As the complexity of board-level systems has grown, Hardware Management systems have begun to consume a disproportionate share of design effort and BOM costs. Now, a distributed Hardware Management architecture is available which connects a control PLD to low-cost sensing elements through a 3-wire serial link. In addition to reducing design complexity, board space requirements and BOM costs, this architecture may be implemented with a wide variety of tools, commonly used by power and digital designers. For Further Reading: "Revolutionary Hardware management Solutions", A Lattice Semiconductor White Paper, April 2015 http://www.latticesemi. com/view_document?document_ id=51004 L-ASC10 Data Sheet - http:// www. l a t t i c e s em i . c om/ v i ew_ document?document_id=50120 "Adding Scalable Power and Thermal Management to MachXO using L-ASC10" A Lattice Application Note http://www.latticesemi.com/view_ document?document_id=50995

functions (Power and temperature management as well as control path and housekeeping functions are collectively referred to as hardware management function). Lattice Semiconductor's L-ASC10, is a Hardware Management (Power, Thermal, and Control Plane Management) Expander. It can be used in conjunction with Control PLDs such as Lattice's low-cost MachXO2 series to implement the Hardware Management function in a circuit board. Figure 6 illustrates how the Hardware Management functionality would be divided up between the L-ASC10 and its companion MachXO2 Control PLD. Each of the analog sense channels is monitored through two independently programmable comparators to support both high/low and in-bounds/out-of- bounds (window-compare) monitor functions. Communication between the ASC and the Control PLD is accomplished through a single 3-wire serial bus (Tx/Rx/Ck). As we'll see in the following scenario, using a single serial bus to monitor and control multiple power supplies greatly reduces both the number of I/O pins required for the PLD. In a distributed Hardware Management architecture, the Control PLD uses several external ASC devices to monitor supply voltages. The Control PLD also transmits Enable/Disable commands to the DC-DC supplies and performs other housekeeping functions. Both Power Management & housekeeping functions can be implemented using a GUI tool, VHDL/Verilog, or a combination of both. PROs: • Common 3-wire bus requires the minimum number of Control PLD I/O pins. • Simplified PCB traces create

debug times. In order to overcome issues with inaccurate Power-Good signals, it's possible to monitor the board's supply voltages using a Control PLD that's equipped with an on- chip digital converter (ADC). In this architecture, the Control PLD implements the power management functions using an on-chip soft/hard processor core while housekeeping functions are implemented in hard logic (Fig.4). For these types of designs, the designer usually develops the Power Management function in software and the other housekeeping functions using VHDL/ Verilog. Pros: • The solution can be easily scaled or adapted for other designs. • Combining Power Management and housekeeping functions reduces design time. • This architecture can provide voltage telemetry to a remote system manager. Cons: • Requires a larger CPLD with higher density and I/O pin count. • Complex CPLD increases solution cost. • Routing low-voltage analog telemetry to a single location increases circuit board congestion. • Forces a digital engineer to implement both power management function as well as digital control functions. Introducing a Distributed Power Management Architecture A Distributed Power Management architecture eliminates the need for many of these trade-offs through the use of a low-cost Analog Sense and Control (ASC) power management element. These devices enable the implementation of complete hardware management

New-Tech Magazine Europe l 31