New-Tech Europe Magazine | August 2017

25 to 250Hz with the most common being between 50 and 150Hz. Higher frequencies result in higher power consumption and ghosting while lower frequencies can cause flicker. Clock sources The three possible clock sources on these modules are usually fast internal RC (FRC) oscillator, secondary oscillator (SOSC) and internal LPRC oscillator. However, for some devices the clock sources are the system clock, the timer one oscillator and the internal RC oscillator. Fig. 2 shows how a clock is typically generated for the LCD peripheral. For the three clock sources, a divider ratio provides about a 1kHz output. For example, if the clock source is an 8MHz FRC oscillator, it has to be divided by 8192 to produce an approximate 1kHz output. This divider is not programmable. Instead, the LCD prescaler bits of the LCDPS register are used to set the frame clock rate. These bits determine the prescaler assignment and prescaler ratio. Typically, two of the three clock sources may be used discretely to continue running the LCD while the processor is in sleep mode. Waveforms An LCD can be characterised by the MUX ratio and bias, but one piece of information is still missing – drive waveforms. LCD waveforms are generated so that the net AC voltage across the dark pixel should be maximised and the net AC voltage across the clear pixel minimised. The net DC voltage across any pixel should be zero. LCDs can be driven by type A or type B waveforms. In a type A waveform, the phase changes within each common type whereas a type B waveform’s phase changes on each frame boundary. Thus type A waveforms maintain 0V DC over a single frame and type B waveforms take two frames. Fig. 3

Fig. 1: Typical LCD module block diagram

Data block Like the timing control block, the data block in Fig. 1 is also present in all these PIC LCD modules. It is composed of the LCDDATAx registers. After the module is initialised for the LCD panel, the individual bits of the LCDDATAx registers are cleared or set to represent a clear or dark pixel, respectively. Specific sets of registers are used with specific segments and common signals. Each bit represents a unique combination of a specific segment connected to a specific common. Bias generation block There are two main methods of generating the bias voltages – resistor ladder and charge pump – both of which can be externally or internally supported by the device. The LCDref register determines whether external or internal resistor biasing is used. Setting the LCDIRE bit enables internal biasing. When internal reference is enabled, contrast can be software controlled by configuring the LCDCST bits, which on some devices are found in a separate

register. The power source for the contrast control can be selected through the LCDIRS bit. The LCDref register also determines which bias pins are used internally or externally for the different bias levels. The LCDRL register provides control for the different ladder power modes, as well as the time interval for each power mode. Using the charge pump method requires only the LCDreg register to be configured. When the charge pump is enabled, contrast can be controlled through the bias bits. The regulator supports either 1/3 or static bias by setting or clearing the relevant bit. The regulator also has to be provided with its own clock source through CLKSEL bits. Frame frequency The LCD frame frequency is the rate at which the common and segment outputs change. The clock source depends on the configured clock source select bits on the device used; PIC MCUs typically have three clock source choices for the LCD module. The range of frame frequencies is from

New-Tech Magazine Europe l 39