New-Tech Europe Magazine | April 2017

Test & Measurement Special Edition

passes over an optional termination directly to a fast sampler with >15 GHz analog bandwidth. The sampler uses sample frequency fS to obtain the signal value and holds it until the downstream ADC has converted the value. The HDMI-specific portion of the TDA module consists mainly of the clock recovery unit (CRU). The clock TMDS_CLK with frequency fTMDS_ CLK is in a fixed ratio to the data TMDS_Dx with bit rate fTDMS_DATA. The ratio is different for HDMI 1.X and HDMI 2. The allowed frequencies and bit rates are summarized in Table 1. The ratio between the bit rate fTMDS_DATA and the clock fTMDS_ CLK is also known as the serialization factor. As seen in Table 1, the CRU must work with a wide range of possible input frequencies. The HDMI specification precisely specifies the transfer function for the CRU. According to the standard, a PLL with the following transfer function is required: H(jω)=1/(1+j ω/ω 0 ) ,ω 0 =2π∙4.0MHz Equation 2 1: Jitter Transfer Function for ideal recovery clock definition

automatically selects one of the four TMDS differential pairs and connects it via the cable to the TDA module, saving the user from having to move the connection. The equalizer and amplifier compensate for the cable frequency response. The TMDS wires

must be terminated appropriately for both AC and DC. The probe ensures the correct termination. The block diagram for the TDA module is shown in Fig. 7. The differential input signal TMDS_ Dx+/– from the HDMI TPA adapter

HDMI 1.X 25…340 0.25…3.4

HDMI 2 85…150

/MHz

f TMDS_CLK f TMDS_DATA f TMDS_DATA

/Gbit/s

3.4…6

/f

TMDS_CLK 40 Table 1: Frequencies and data rates for HDMI 10

Fig. 7: Block diagram of the base module

Fig. 2 1: TMDS clock jitter measurement

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