November_EDFA_Digital

ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 20 NO. 4 62 FAILURE ANAMNESIS: THE SYSTEM CHALLENGE IN FA AND RELIABILITY Peter Jacob, EMPA Dübendorf, Center for Electronics & Reliability, Switzerland peter.jacob@empa.ch W hen discussing a SWOT (Strengths, Weaknesses, Opportunities, and Threats) evaluation of any failure analysis, the evergreen question of “THESE EXPERTS NEED AN INTERDISCIPLINARY KNOWLEDGE BASE OF APPLICATIONS, SYSTEMS, CIRCUITRY, AND PROCESSES AROUND SOLDERING AND PCBS.” GUEST COLUMNIST

whether FA techniques in the future will cope with the latest miniaturization steps always comes up. In fact, the development of localization techniques, FIB, magnetic microscopy, and other new technologies is amazingly— though sometimes barely—keeping pace with FA needs. However, our technical community is faced with another creeping threat: Electronics in systems are grow- ing—and growing everywhere. Cars, planes, elevators, escalators, refrigerators, stoves, and numerous other appliances, which in former times had few electronics inside if any, are now equipped with a huge amount of electronics. For the failure rate of the single electronic device, this spreading of ever more complex electronics calls for a tremendous increase in reliability—not only for semiconductor devices, but also for passive components and packaging/interconnect technologies including printed circuit boards (PCBs) and overvoltage protection concepts. In the very near future, a failure analysis will not be limited to just analyzing failed semiconductor devices. As long as we are not talking about a semiconductor process accompanying failure analysis, device-related FAwill become just a small brick, an input to the root cause finding. Those in our community dealing with customer returns know firsthand that most field returns are based on out-of-spec operations, in-process treatment, specifi- cation gaps between supplier and user, and interconnect technique issues fromPCB to device, while only a fraction of those returns relate to semiconductor device produc- tion failures. At EMPA, our customers looking for failure analysis support come from nearly everywhere in the supply chain—from device manufacturers to complete system vendors. They expect root cause findings fromus and not just electrical overstress (EOS) conclusions. (Jokesters

among us say EOS = end of story.) To cope with this challenge, we developed and apply a comprehensive FA approach, which we refer to as failure anamnesis —a term equivalent to the medical meaning. If you ask for medical advice when you suffer from a stomachache, a good physician will not just give you a pain reliever and charcoal tablets. Hewill askwhat you’ve eaten in the last few days, check on allergies, and ask a lot of questions about your former diseases, whether you experienced stress, and other issues. He may do some investigations you never would have expected. The physi- cian wants to understand your pain in whole and not just handle symptoms. This approach is exactly what we as failure analysts need to copy—to look at the system as a whole. While device failure analysis starts from the bottom level of the system (the failed device), failure anamnesis starts at the top—at the system itself. It is nice to localize and TEM- investigate a gate ox breakdown—but thereafter, do we really knowwhat caused it? Ending theworkwith frequent conclusions such as “EOS/ESD” helps no one. Starting from the headline question—“How was the system failing”—we ask and evaluate a lot of questions around system-related operating conditions, failure statistics, and circumstances. Also, a careful evaluation of circuitry around the failed device on possible missing overvoltage protections, inductance loads, EMI risks,

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