New-Tech Europe | Aug 2019 | Digital Edition

A 3D technology toolbox in support of system-technology co-optimization Julien Ryckaert & Eric Beyne, Imec

System-technology co-optimization (STCO) – enabled by 3D integration technologies – is seen as a next ‘knob’ for continuing the scaling path. Eric Beyne, imec fellow and program director of imec’s 3D system integration program and Julien Ryckaert, program director 3D hybrid scaling at imec, unravel the STCO principle, open up the 3D technology toolbox and bring up two promising cases: logic on memory, and backside power delivery. After DTCO comes STCO... For many years, the semiconductor industry has lived in an era of ‘happy scaling’ – driven by the Law of Gordon Moore. In this era, dimensional scaling alone could provide each new technology generation with the required power- performance-area-cost benefits. But the last 15 years, the chip industry has not been following that happy

scaling path anymore. Dimensional scaling started to provide diminishing returns, marking the end of that era. Fromthe 10nmtechnology generation onwards, traditional scaling has been complemented by design-technology co-optimization (DTCO), combining expertise from technology as well as from design. In this DTCO era, track height reduction and a growing number of structural scaling boosters have been introduced, allowing to scale standard cells and static random access memories (SRAMs) to an extreme level of compactness. Scaling boosters include, for example, self-aligned gate contact, metal-gate cut and supervia. But as we move further and look at the benefits of what DTCO can bring at system-on-chip (SoC) level, we can expect a certain saturation – especially when we start considering global access and power delivery to the SoC.

Therefore, for 3nm and beyond technology nodes, we will need to shift focus from scaling at logic cell level towards scaling at system level. Hence, DTCO is evolving into an STCO-oriented approach. STCO: a clever way of disintegration In general, STCO involves the disintegration and reintegration of a SoC. A SoC is composed of various (heterogeneous) sub-systems (functions) that are interconnected by a complex wire scheme. When disintegrating a SoC, it should be decided in a clever way at what level in this wiring interconnect hierarchy the system is cut into different partitions. But how can this be done? What components belong together, and which should be processed separately? Most often, a trade- off is to be made between the

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