New-Tech Europe | Aug 2019 | Digital Edition

the wafer’s back-end-of-line – which is at the front-side of the Si wafer. We can also envision to provide the global power from the backside of the wafer. From there, this network of interconnects can connect to a buried power rail, a scaling booster in the form of a local power rail that is buried in the chip’s front-end-of-line. In practice, this backside processing can be done by first hooking the CMOS processed wafer onto a carrier using wafer-to-wafer bonding. Then, the wafer’s backside is thinned down with an extreme level of thinning – to about a few 100nm. This allows to expose nm-scale through-Si vias that run from the wafer frontside to the backside and connect them with extremely fine granularity. By directly delivering power to the standard cells through the backside, the imec team recently demonstrated a 30% area scaling benefit. In addition, implementing the power delivery network in the backside can relieve the frontside (i.e., the back-end-of- line or BEOL) from power routing, which reduces the BEOL complexity. It also improves the supply voltage drop (or IR drop, which is caused by a resistance increase in the back- end-of-line), providing up to 15% performance enhancement. It is interesting to note that this concept of functional backside processing can be extended beyond power delivery. One can start thinking of implementing other functions within the wafer’s backside, including, for example, metal- insulator-metal (MIM) capacitors, electrostatic discharge (ESD) devices or indium-gallium-zinc-oxide (IGZO) transistors. In summary... With DTCO running out of steam, we are now at the eve of a new age: the era of STCO – where scaling at logic cell level will be complemented by scaling at a global system level. STCO

Figure 4: Backside power delivery network: first hardware demonstration

involves the SoC to be disintegrated, and subsequently reintegrated by using one of the available 3D integration technologies. These technologies can be applied at different levels of the 3D interconnect hierarchy, from the package to the die, to the wafer, to the standard cell and even to the transistor level. Two cases – logic on die, and backside power delivery – illustrate how this STCO framework is now also penetrating the logic world – providing further knobs for continuing the scaling path. About Julien Ryckaert Julien Ryckaert received the M.Sc. degree in electrical engineering from the University of Brussels (ULB), Belgium, in 2000 and the PhD degree from the Vrije Universiteit Brussel (VUB) in 2007. He joined imec as a

converters. In 2010 he joined the process technology division in charge of design enablement for 3DIC technology. Since 2013, he is in charge of imec’s design-technology co-optimization (DTCO) platform for advanced CMOS technology nodes. He is now program director focusing on scaling beyond the 3nm technology node as well as the 3D scaling Eric Beyne obtained a degree in electrical engineering in 1983 and the Ph.D. in applied sciences in 1990, both fromtheKatholiekeUniversiteit Leuven, Belgium. Since 1986 he has been with imec in Leuven, Belgium where he has worked on advanced packaging and interconnect technologies. Currently, he is imec fellow and program director of imec’s 3D system extensions of CMOS. About Eric Beyne

mixed-signal d e s i g n e r in 2000 s p e c i a l i z i n g in RF transceivers, u l t r a - l o w power circuit t e c h n i q u e s and analog- t o - d i g i t a l

i n t e g r a t i o n program. He received the European Semi Award 2016 for contributions to the development of 3D technologies.

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