New-Tech Europe Magazine | Q1 2023

microseconds. This creates stress across the PDN of a high-performance processor module or accelerator card. The architecture of a typical power delivery network is highlighted in Figure 2. Best practices for optimizing the power delivery network The work by the Open Compute Project® (OCP®) consortium has helped establish a framework of standards for designing rack- and card-based processor developments. The Open Rack Standard V2.2 defines a 48V server backplane and a 48V operating voltage for open accelerator modules (OAMs) used predominately for artificial intelligence (AI) and machine learning workloads. To maintain compatibility with legacy 12V systems, the standard stipulates the ability to meet 12-to-48V and 48-to-12V requirements. Focusing on powering the processor, or PoL, is fraught with technical challenges. The technical advances highlighted in the previous section focused on the downward trend of voltage scaling, the requirement for tight core voltage tolerance and the upward trend of current consumption. At the board level, the impact of these factors manifests in multiple ways. The peak cur ren t dens i t i es encountered are extreme for any PCB. Routing power paths capable of these huge loads demands careful attention. Highly dynamic workloads can create spiking voltage transients, which sophisticated processors find disruptive and potentially damaging. Yet, a processor board has hundreds of other passive components, memory and other ICs essential to its operation that also need placement. Then there are the I2R losses. Power path trace lengths need to be short. To achieve this the power conversion

Figure 1: In most cases, power delivery is now the limiting factor in computing performance as new processors consume ever increasing currents. Power delivery entails not just the distribution of power but also the efficiency, size, cost and thermal performance.

Figure 2: Typical high-performance processor PDN

New ideas, architectures, topologies and technologies are the path to a more reliable, scalable power delivery network. The Vicor Factorized Power Architecture (FPA™) is the foundation for delivering more efficient power for today’s unprecedented high performance computing demands. The Vicor FPA divides the task of a power converter into the dedicated functions of regulation and transformation. A high-efficiency, high-density solution is achieved by separating them and optimizing them individually. FPA in conjunction with the Sine Amplitude Converter (SAC™) topology underpins several

modules should be close to the processor to reduce trace heating. The likelihood of PCB flexing due to the processor load currents and localized thermal gradients of the processor demand board stiffeners. Also, the converter's power efficiency specification should be as high as possible to prevent further thermal management challenges. Unleashing the power of the processer Delivering enough power to the processor today needs innovation to try to get ahead of the status quo.

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