New-Tech Europe | Q3 2026 | Digital Edition

Figure 2: Si-Fly HD is available in several configurations designed to provide high-density connectivity for 224 Gbps PAM4 architectures. Credit: Samtec

ASICs may require hundreds of high-speed I/O connections within an extremely restricted physical area. In this architecture, moving the interconnect closer to the silicon therefore solves two problems simultaneously: it shortens the high-speed electrical channel and increases the connection density available around the device. Designing the connection at package level Moving the connector from the PCB onto the package substrate changes more than the electrical path. It also changes the mechanical and assembly requirements of the interconnect. For its Si-Fly HD architecture, Samtec uses a Column Tail structure designed for direct attachment to the package substrate. According to the company, the approach is intended to improve connection uniformity and connector coplanarity while maintaining mechanical stability through the reflow process. Once the connector is attached to the substrate, the cable assemblies can be installed, followed by the thermal solution required by the particular system architecture. This sequence illustrates an important consequence of Co Packaged Connectivity: high-speed I/O, power delivery, mechanical integration and cooling increasingly have to be considered together rather than as independent design tasks. From simulation to measured performance Reducing the theoretical channel length is only useful if the resulting interconnect can maintain the required electrical performance at 224 Gbps PAM4. Samtec therefore compared Si-Fly HD performance against

cannot remove the package and PCB structures that remain between the ASIC and the cable. Moving the interconnect onto the package The next architectural step described by Samtec is Co Packaged Connectivity. Instead of mounting the high-speed connector on the PCB near the ASIC, the connector is mounted directly onto the package substrate. This allows the signal path to bypass significant portions of the conventional BGA and PCB routing structure. The electrical benefit is substantial. Every via, solder-ball transition and PCB structure that can be removed from the channel also removes a potential source of loss, reflection or impedance discontinuity. According to Samtec’s analysis, its Co-Packaged solution can provide a channel-loss improvement of up to 3 dB by avoiding losses associated with the package via/ball and PCB routing. At 224 Gbps PAM4, where the available channel budget is increasingly constrained, recovering several decibels is not a marginal improvement. It can materially change the feasibility of the channel. Co-Packaged Connectivity also addresses another problem: density. Samtec compares conventional Near-Chip solutions with its Si-Fly HD Co-Packaged architecture. While a typical Near Chip implementation provides approximately 60 differential pairs per square inch, the Si-Fly HD architecture can reach approximately 170 differential pairs per square inch. The increase is important because the challenge is not simply transporting one 224 Gbps channel successfully. Modern

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