New-Tech Europe Digital Magazine | May 2016

Figure 4 – Block diagram of Zynq SoC implementation

of 550 nanoseconds in each node of the ring and integrates internal and external trispeed Ethernet ports. The internal port is sniffed and time- stamped by the Precise Time Basic (PTB) IP core, providing support for the PTP stack. This IEEE 1588v2 infrastructure allows the smart gateway to work as master, slave, transparent clock and boundary clock. Thus, at the end, in each piece of equipment a synchronized 64-bit timer can be used for time-stamping, synchronization, control and as a common time reference to implement Time-Sensitive Networking (TSN) networks. These networking cores implemented on the FPGA section of the Zynq SoC are also ready to support cybersecurity features such as IEEE 802.1X authentication. This mechanism, combined with an external authentication server, protects nonauthorized connections to the network ports. The Zynq SoC’s programmable logic also plays a vital role in securing Layer

Figure 5 – Software infrastructure for the smart-factory network

4 is a block diagram of the SoC implementation for the CPPSGate40 in the Microdeco implementation. The network’s switching infrastructure is coordinated by the SoC-e HSR/ PRP/ Ethernet switch (HPS) IP core, which ensures a constant forwarding time

challenges these applications present. From the hardware perspective, the Zynq SoC’s programmable logic is the perfect candidate to implement the low-latency networking tasks combined with the IEEE 1588v2 hardware support units. Figure

50 l New-Tech Magazine Europe