New-Tech Europe Magazine | Aug 2018

The potential of sequential-3D integration for avanced semiconductor scaling

Nadine Collaert, IMEC

Sequential-3D is perceived as a promising alternative to continue the benefits offered by semiconductor scaling. Nadine Col-laert (distinguished member of technical staff at imec) and her team review the technology integration challenges and the potential ben- efits of this emerging integration technology. Intro Technology innovations are expected to allow traditional Moore’s Law scaling for logic and memory applications to continue for at least five to ten years. At the same time, researchers worldwide are exploring alternative options to overcome a number of challenges – physical, technological and economical – associated with further scaling of CMOS transistor dimensions. One of integration

these alternatives is sequential-3D integration (S3D), a relatively new technology that promises to alleviate problems in classical 2D CMOS. This integra-tion technique involves the vertical integration of sequentially pro-cessed device layers, and comes in three different flavors – depend- ing on where the partitioning and stacking takes place. “One of these alternatives is sequential-3D integration (S3D), a relatively new technology that promises to alleviate problems in classical 2D CMOS.” Three different S3D flavors Firstly, in transistor-level S3D, the CMOS gate is split into tiers of pMOS and nMOS. Secondly, in CMOS-level

S3D, conventional 2D standard cells are placed in different tiers. And finally, the partition-ing can be done at IP block level to separate, for example, the ana-log and I/O functionality from the logic and memory part. This is referred to as hybrid S3D (or heterogeneous S3D) where besides CMOS devices, different flavors of technologies can be combined. Technology integration challenges S3D comes with its own set of technology challenges, mainly caused by the limited thermal budget that is available for processing the top and bottom tiers. Imec has proposed innovative solutions for pro-cessing the interconnect metals, the device contacts and gate stacks. With these

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