New-Tech Europe Magazine | Aug 2018

solutions, the technique is expected to further enhance device density per chip area, reduce the length of the inter-connection lines, and facilitate the co-integration of heterogeneous device technologies. Potential benefits To quantify the true benefits, the imec team has performed a sys- tematic power-performance-area- cost analysis for each of the S3D flavors. “As a main conclusion, the largest benefit is found for a het-erogenous S3D case, where the logic and memory part is using a scaled technology, and the remaining non-scalable part (analog in combination with I/O) is manufactured in a more relaxed 28nm technology in the top tier.” S3D is found to be less straightforward for dimensional scaling (i.e., S3D at transistor or cell level). The relative benefits are however largely dependent on the technology assumptions and on the com-ponent distribution. A typical application of a S3D implementation can be stacked SRAM cells, where transistors of neighboring cells are stacked on top of each other. The hybrid S3D approach will e.g. benefit the implemen-tation of next-generation application hardware such as 5G and ma-chine learning. Biography Nadine Collaert Nadine Collaert received an M.S. and Ph.D. degree in electrical engi-neering from the ESAT Department, KU Leuven, Belgium, in1995 and2000, respectively. Since then, she has been involved in the theory, design and technology of FinFET devices, emerging memory devices, transducers for biomedical

Figure 1: Sequential-3D (a) at transistor level and (b) at cell level

applications and the integration and characterization of biocompatible materials (e.g. carbon-based materials). From 2012 until April 2016 she was program manager of the imec LOGIC program, focusing on high mobility channels, TFET and nanowires. Since April 2016 she has been a distinguished mem-ber of technical staff, responsible for the research on novel CMOS scaling approaches based on heterogeneous integration of new ma-terials with Si and new material-enabled device and system ap-proaches to increase functionality.

Nadine Collaert

Figure 2: Illustration of hybrid S3D. In this example, the logic and memory part is scaled to the 3nm (or iN5) node in the bottom tier, and the remaining part (analog and I/O) is manufac-tured in the 28nm technology node in the top tier. In this particular case, the non-scalable analog and I/O part takes up to 30% of the overall circuit area.

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