New-Tech Europe Magazine | Aug 2018

Connector Designs To Address Data Rate and Density Challenges Kris Erickson, Danny Boesing, Samtec, Inc.

As the need for bandwidth continues to increase, so does the need for higher data rates within a system. What was once one to three Gbps, then moved to 4 to 8 Gbps, and then we saw the jump to 16 G, and now we are approaching 28 Gbps and looking forward to 56 G. This trend was recently driven home at DesignCon 2018, where many exhibitors were demonstrating interconnects running at 112 Gbps PAM 4. 56 Gbps, which had been the focus of previous shows, received much less attention. Although the Datacom and Telecom industries are abuzz pushing these cutting-edge data rates, achieving this performance is much easier said-than-done. Design challenges include routing complexities on the PCB and the potential need for

higher layer counts. For longer trace lengths, more exotic PCB materials with lower dielectric constants and re-timers are incorporated to mitigate degrading signal loss. All of these factors add more cost to the system. Besides materials and costs, designers also frequently face challenges with the decreasing size of the finished products. The proliferation of mobile and hand- held devices drives this trend, as well as new requirements in industries such as telecom, high- power computers, medical devices, aerospace and defense, and even industrial applications. In addition, new high data rate chipsets, which of course are designed to generate as little heat as possible, still produce heat. These

often require more and bigger heat sinks, further complicating the design dilemma. Obviously, the increasing demand for smaller, higher bandwidth PCBs pushes R&D in the interconnect industry. Sales of both micro pitch and high-speed interconnect systems steadily increase. The interesting caveat is most high- speed interconnects are also micro pitch. But, the smaller the pitch of the interconnect, the more difficult it is to achieve higher bandwidths. Smaller and tighter pitch interconnect systems introduce a new set of electrical challenges, such as crosstalk and insertion loss. This is primarily due to the proximity of one differential pair to the next, reduced space for routing, and a reduction in grounds pins.

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