New-Tech Europe Magazine | Q2 2023

What other avenues is imec exploring to support next lithography nodes? “There are several new evolutions ongoing in photomask development. To address the requirement of lowering the EUV exposure dose, masks with low-n absorber are being heavily investigated because they create aerial intensity profiles with high contrast (or NILS) at low exposure dose. At imec, we are also concerned about wafer stochastics and mask 3D effects (i.e., distortions of the aerial image related to the mask 3D topography). Stochastic failures at wafer level have many sources of which mask variability is one. To address the issue, we study which types of mask variability (incl. different roughness’s) are more prone to increased stochastics at wafer level, with the aim of proposing updated mask and blank specs. Also, High NA EUVL scanners will use anamorphic lenses, which provide unequal magnification in the x and y directions. This anamorphicity implies field stitching on wafer level to achieve the same wafer field size as other, conventional optical lithography. Wafer field stitching puts more importance at mask level to the quality of the mask field edge and possible mitigation schemes. Due to the increased importance of a deep understanding of the mask interactions with EUV illumination, at imec, we bring together the full mask R&D ecosystem. Together with our mask and blank suppliers, we support the industrialization of mask innovations (like novel absorbers) and explore mask complexity (like variability or stitching), both in the imec-ASML High NA EUV Lab and through modelling. Due to the increased importance of a deep understanding of the mask interactions with EUV illumination, at imec, we bring together the full mask R&D ecosystem. None of these issues are fundamental showstoppers for the introduction of

cell. When scaling the pitch to increase density, the lateral critical dimension (CD) of the capacitor will continue to shrink and the capacitor needs to be made increasingly tall to keep the capacitance constant. That will lead not only to manufacturing problems and yield loss, but we also expect 2D DRAM to hit fundamental material limits. To overcome these issues, various 3D DRAM flows are being considered and key challenges are being addressed at module level. We will likely see the introduction of new materials such as semiconductor oxides, complemented with the use of several high-aspect ratio etching and lateral recess steps, which are challenging in many ways. Next to that, filling of vertical holes and lateral cavities with liners, dielectrics, and metals are expected to be at least as challenging as today encountered in 3D-NAND-Flash technology.” Moving on to another topic, as your team conducts all process and materials related research at imec: how does imec contribute to a more sustainable manufacturing? “Today, IC manufacturing is estimated to account for about 0.1 percent of global emissions. However, due to the growing complexity of advanced technology nodes, CO2 emissions associated with manufacturing logic technologies are expected to double in the next 10 years. At the same time, the total volume of wafers produced is projected to grow by ~eight percent annually. If we do nothing, emissions associated with IC manufacturing will quadruple in the next decade. According to the Paris agreement, all industry sectors should cut their emissions in half every decade. In other words, in the “do-nothing” scenario, our industry will be off target by a factor eight. That’s why sustainability is a key pillar of imec’s research. We launched our sustainable semiconductor technologies and system (SSTS) program, gathering

High NA EUVL. However, for a smooth, timely and cost-effective introduction of High NA EUV with maximum performance, it is of key importance to address these challenges proactively and to offer to the key players of the ecosystem an effective collaboration platform. The primary motivation of imec and ASML setting up this High NA EUV lab, built around the first High NA scanner, is to facilitate the fastest possible industry introduction and ramp up of High NA EUV lithography.” What other developments will impact the field of patterning in the next two to five years? “In addition to innovations in EUVL, unique patterning opportunities emerge from the rise of new device concepts for both logic and memory that increasingly make use of the third dimension. Complementary FET (CFET) is the future device architecture beyond gate all-around (GAA) nanosheets, exploiting the concept of stacking one FET channel on top of another FET device. The device fabrication requires high-aspect-ratio patterning steps to realize the active part, the gate, source/drain recess, as well as the middle-of-line M0A contact formation. Besides, high amounts of material recess such as metal or dielectric will be imperative. Innovations including bottom-up deposition or area selective deposition (ASD) could play an important role in reducing the process complexity for CFET. Next, to allow CFET-based standard cell scaling from 5-tracks to 4-tracks, the CFET device will likely be integrated with backside power delivery. This new routing scheme will require high-aspect-ratio via opening and self-aligned patterning with good selectivity to the gate spacer. Unique patterning opportunities emerge from the rise of new device concepts for both logic and memory that increasingly make use of the third dimension. In the memory space, DRAM currently relies on a narrow, tall capacitor as a bit

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