New-Tech Europe Magazine | H2 2023

Towards a process flow for monolithic CFET transistor architectures

IMEC

CFET to complete the nanosheet family in the logic technology roadmap Hans Mertens, principal member of technical staff at imec: “Today, the semiconductor industry is in a transition period from FinFET to Nanosheet, a device architecture that will extend the roadmap with multiple logic technology generations. Along the road, we might introduce the Forksheet, an advanced nanosheet architecture that we proposed a few years ago, with reduced separation between adjacent devices, offering both scaling and performance advantages compared to conventional nanosheet. Towards the end of the decade, we expect the complementary FET (CFET) to enter the roadmap. In this device architecture, n- and pMOS devices are stacked on top of each other, removing for the first time the n-p

Imec highlights critical process steps and modules for monolithic CFET devices The development of a process flow capable of demonstrating functionality of a monolithic complementary FET (CFET) transistor architecture is complex due to the need to vertically separate nMOS and pMOS devices within the same footprint. In this interview, Hans Mertens, Steven Demuynck, and Anne Vandooren – three experts from the imec CFET team – explain how they gradually address this complexity. They highlight CFET-specific process steps and modules and introduce backside connectivity as a key technology enabler to further reduce the size of standard cells.

separation from standard cell height considerations. When complemented with advanced technologies to contact the transistors, CFET will allow to gradually push track heights from 5T to 4T and even beyond, effectively shrinking standard cell size substantially. From processing point of view, CFET fabrication is challenging due to the nMOS-pMOS vertically stacked structure, and we are in the early stages of pathfinding. Several flavors of CFETs have been proposed, including monolithic and sequential process flows. In a sequential process flow, top-tier devices are processed sequentially after transfer of a blanket semiconductor layer by wafer bonding on top of bottom tier devices. Monolithic integration, on the contrary, involves building the vertical device architecture on a single substrate.”

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