New-Tech Europe Magazine | H2 2023

Monolithic CFET: the fastest path to CFET introduction

Anne Vandooren, principal member of technical staff at imec: “Within our logic program, imec and its partners focus on monolithic CFET integration, as this integration scheme is the least disruptive compared to existing nanosheet type process flows. It is therefore believed to offer the fastest path to CFET introduction at industry-relevant dimensions. Nevertheless, the vertical stacking of layers from which both devices will be fabricated drives a need for high-aspect ratio patterning, selective deposition and removal of materials, and the deposition of high-quality (epi-)films. In addition, some CFET-specific process modules will need to be introduced to enable vertical isolation in the gate and contact part of the cross-section. We address these challenges by partitioning the monolithic CFET integration challenge into different sub-projects, with gradually increasing integration complexity. Each sub-project builds on a different test vehicle. We first focus on unipolar monolithic CFET, with n and p top and bottom devices processed on different wafers. The other test vehicles will have monolithic CMOS CFET devices processed on the same wafer. They mainly differ in the way the CFET devices are contacted, eventually working towards advanced middle-of-line (MOL) and backside connectivity options. For each of the test vehicles, we explore various process and integration options, trading off power-performance-area gains against complexity. The learnings obtained on each of the vehicles is transferred to the next.” Unipolar monolithic CFET demonstration at 48nm gate pitch Hans Mertens: “At VLSI 2020, imec was the first to demonstrate monolithic CFET devices on a 300mm wafer, although at a ‘relaxed’ gate pitch (i.e., contacted

Figure 1: End-of-process cross sectional images for (a) bottom pFET and (b) top nFET (LG,PHYS=27nm) (as presented at VLSI 2023). Credit: IMEC

poly pitch (CPP)) of 90nm. At VLSI 2023, imec presented unipolar CFET devices built through monolithic integration at industry-relevant 48nm gate pitch [1]. This work was selected for the 2023 VLSI Technology Symposium Highlights session. Our functional devices showed excellent switching characteristics for bottom and top devices separately, for both n- and pMOS. We are currently exploring unipolar monolithic CFET integration at even smaller gate pitch. In this demonstration, the source-drain epitaxial structures (source-drain epi) and source-drain contacts are evaluated for either bottom or top devices. In addition, to limit the aspect ratio and be faster in the development, the active part of the structure was limited to only one nanosheet for the bottom and one for the top device. The significance of this work, however, is to show that, with a vertical separation of only 30nm between top and bottom sheets, we found a way to independently contact top and bottom devices. It is a steppingstone for advanced CFET integration at scaled dimensions.” Monolithic CMOS CFET: challenging process steps and modules Steven Demuynck, scientific director at imec: “In addition, we continue our efforts to enable monolithic CMOS CFET device demonstration, a project

strategic to imec, enabled by intense collaboration with our partners. Unlike for the unipolar CFET devices, stacked p-bottom and n-top devices will now be implemented on the same wafer and contacted independently. In addition, the integration flow should allow differentiating the threshold voltage (Vt) setting on the two devices that share a common gate – all at an industry relevant gate pitch of 50nm. This vertical architecture has major implications. It requires not only the development of three new, CFET-specific process modules, but also adjustments to the other modules in the process flow to accommodate the presence of these CFET-specific modules. A first CFET-specific process module, which we refer to as the middle dielectric isolation (MDI), stems from the need to create a vertical dielectric isolation between top and bottom gate to differentiate on the Vt setting between top and bottom devices. To enable this, our team proposed a unique solution that affects the process flow from the start: the Si/SiGe stack, formed to create the active part of the CFET, is turned into a taller Si/SiGe1/SiGe2 multilayer stack, with higher Ge% for SiGe2 than for SiGe1. While sacrificial SiGe1 layers are replaced with the work function metals setting the Vt, the Ge-rich sacrificial layers are converted into the MDI dielectric creating

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