New-Tech Europe Magazine | H2 2023

the n-p WF metal separation within the gate. The stack allows for the formation of an inner spacer on the Ge-deficient layer in the stack – a critical nanosheet specific feature that isolates the gate from the source-drain. Finding the most efficient way to co-integrate the bottom source-drain, the new MDI module and inner spacer at this tight pitch and for high aspect ratio geometries is currently the focus of our R&D effort. A second vertical isolation is needed between the source-drain contact metals of the top and bottom devices. Various options are explored to build and isolate bottom and top contacts – deep in between two tall gates – and subsequently route bottom and top transistors. A morphological proof of concept flow demonstrating the capability to fabricate a stacked MOL was shared at VLSI 2023 [2]. And finally, we need to encapsulate the top channel when growing the source drain epi on the bottom device. This will effectively enable growing differentially doped epi on bottom and top devices.” Connecting the CFET devices from the backside Anne Vandooren: “On the longer term, we are exploring advanced integration options to connect the active devices from the backside. The developments are driven by the need to further reduce standard cell heights and avoid routing congestion in the back-end-of-line at the frontside of the wafer. Backside contacting introduces additional process steps, including wafer bonding and substrate thinning from the backside. These steps challenge a very tight overlay for aligning the backside layers to the small features already present in the frontside. This is even more challenging as wafer deformation occurs during bonding, requiring the use of specific litho overlay correction methods. In addition, an extra process module is needed to provide proper isolation between the backside metal 1 and the active nanosheet part of

the CFET device.” CFET enablement: an industrial collaboration effort Steven Demuynck: “Since we started CFET development, we have been seeing an increase in the intensity of engagement with our equipment suppliers. On the one hand, these vendors want to be involved in a very early stage of development to be able to identify where their tools, processes, and materials may fit into this roadmap. They also want to understand the context in which these would need to operate, to create awareness of interactions up and downstream in the flow. Imec plays a pivotal role in supplying these companies with wafers that have CFET-relevant topologies and geometries. Such material is usually not readily available to them before development begins at IDMs. On the other hand, these collaborations bring benefits for imec as well. The collaboration with our tool vendors helps us tap into the most advanced capabilities of our partners. In parallel, our logic core partners take an interest in identifying the key challenges and potential roadblocks that we encounter by evaluating various flow flavors. Understanding at an early stage what hardware and processes are enabling, can give them a head start in embarking on a R&D effort on their part.” Want to know more? [1] ‘Nanosheet-based complementary field-effect transistors (CFETs) at 48nm gate pitch, and middle dielectric isolation to enable CFET inner spacer formation and multi-Vt patterning’, H. Mertens et al., VLSI 2023; [2] ‘Integration of a stacked contact MOL for monolithic CFET’, V. Vega-Gonzalez et al., VLSI 2023. Interested in receiving these papers? Fill in our contact form. About the authors Steven Demuynck received a M.S degree in physics from K.U. Leuven (1994) and a Ph.D. degree in physics from KU Leuven,

Belgium, in 2000. He joined imec in 2001, where he is currently scientific director. In this role, he is driving the integration effort aimed at demonstrating functional CMOS monolithic CFET on Sigma2. Anne Vandooren received her M.S. degree in electrical engineering from the Université Catholique de Louvain (UCL) in Belgium in 1996, and her Ph.D. degree in electrical engineering from the University of California, Davis in 2000. From 2000 to 2007, she was a senior researcher at Motorola/Freescale working on the integration of FDSOI and FinFET technologies. She joined imec in 2007, where she is principal member of technical staff. In this role, she focuses on the development of novel CFET architectures including monolithic and sequential approaches as well as backside connection. Hans Mertens received a M.S. degree in applied physics from Eindhoven University of Technology (2002) and a Ph.D. degree in physics from Utrecht University (2007), both in The Netherlands. From 2007 to 2012 he was a senior scientist at NXP Semiconductors, working on SiGe heterojunction bipolar transistors for RF applications. He joined imec in 2012, where he is a principal member of technical staff. In this role, he focuses on exploring novel integration solutions for advanced CMOS transistor architectures, including CFETs.

From left to right: Steven Demuynck, scientific director at imec; Anne Vandooren, principal member of technical staff at imec; Hans Mertens, principal member of technical staff at imec.

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