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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 3 4 EDFAAO (2019) 3:4-6

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Xe PLASMA VS. GALLIUM FIB DELAYERING Sharang Sharang, Tescan Brno, s.r.o., Czech Republic Paul Anzalone, Tescan USA Inc., Warrendale, Pennsylvania Jozef Vincenc Obona, Tescan Orsay Holding a.s., Czech Republic

INTRODUCTION Layer-by-layer deprocessing is becoming increasingly vital and challenging for industrial and research applica- tions such as failure analysis, chip reverse engineering, and patent violation detection. Gallium focused ion beam (Ga FIB) and Xe FIB instruments are the go-to tools for chip material analysis in the semiconductor industry for applications like transmission electronmicroscopy (TEM) lamella preparation, circuit edit, and cross-sectional analysis. A common technique for delayering is mechani- cal polishing, which is not precise or localized enough in removing sensitive layers on IC chips. [1,3] Previously these researchers have used a Xe FIB successfully for delayer- ing on sub-14 nm technology from metal 8 to transistor contacts in combination with special gas chemistry. [4] This article shows that a Ga FIB with the same chemistry as the Xe FIB can also performdelayering on a sub-14 nm technologymicroprocessor and discusses the differences between the two use cases. EXPERIMENT DETAILS AND RESULTS Top-down delayering of sub-14 nm technology nodes was performed with both Ga and Xe FIBs using A-Maze special gas precursor (proprietary gas chemistry of Tescan Orsay Holding a.s.). Figure 1a shows a 100 × 100 µm² area opened on sub-14 nm using Xe FIB by aligning the sample analytical working distance to the SEMpositioned orthogonal to the FIB beam. A GIS was inserted to inject A-Maze gas onto the area of interest. Suitable current density and beam shape were used to conduce planar- ity in the presence of the gas chemistry. The process was monitored using end point detection based on the SE signal being generated during the etching process (Fig. 3). The end pointing recognizes peaks as the metal layer and troughs as the via layer, which gives full control to theoperator to start and stop theprocess onany layer of interest. Fine polishing is performed once a specific layer is reached to get rid of residual metal/dielectric from the previous removed layer. Figure 2a shows a 20 × 20 µm²

Fig. 1a Delayeredwindowwith Xe FIB to transistor contacts.

Fig. 1b Nanoprobes performing electrical measurement on a PMOS.

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