August_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS An ASM Materials Solutions Publication

AUGUST 2019 | VOLUME 21 | ISSUE 3

A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS

IN THIS ISSUE...

LARGE AREA AUTOMATED DEPROCESSING OF INTEGRATED CIRCUITS: PRESENT AND FUTURE RECENT ADVANCES IN VLSI CHARACTERIZATION USING THE TEM

Xe PLASMA VS. GALLIUM FIB DELAYERING

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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS An ASM Materials Solutions Publication

AUGUST 2019 | VOLUME 21 | ISSUE 3

A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS

IN THIS ISSUE...

LARGE AREA AUTOMATED DEPROCESSING OF INTEGRATED CIRCUITS: PRESENT AND FUTURE RECENT ADVANCES IN VLSI CHARACTERIZATION USING THE TEM

Xe PLASMA VS. GALLIUM FIB DELAYERING

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DEPARTMENTS 2 GUEST EDITORIAL Ian A. Young 34 SPECIAL ISTFA PREVIEW Felix Beaudoin 36 ISTFA EXHIBITORS LIST 38 2019 PHOTO CONTEST 39 2019 VIDEO CONTEST 40 DIRECTORY OF FA PROVIDERS Rose Ring 42 PRODUCT NEWS Ted Kolasa Failure analysis without a transmission electron micro- scope (TEM) has become almost unthinkable in modern semiconductor manufacturing. This article reviews recent advances that transformed the TEM from a pure imaging tool into a versatile instrument for physical and composi- tional characterization. Large Area Automated Deprocessing of Integrated Circuits: Present and Future E.I. Principe, Z.E. Russell, S.T. DiDona, M. Therezien, B.W. Kempshall, K.E. Scammon, and J.J. Hagen Recent achievements and present limitations of large area automated deprocessing of integrated circuits are discussed in this article. It also describes future integrated circuit deprocessing tool development related to purpose- built laboratory-based hardware and synchrotron-based instrumentation. Failure Analysis for Hardware Assurance and Security M. Tanjidur Rahman and Navid Asadizanjani This article presents a comprehensive study of different physical inspection/attacks, the prospect and challenges of physical inspection methods as an emerging trust verification tool, and the dire threat imposed by physical attacks on systems on chip. This article shows that galliumfocused ionbeam(FIB) with the same chemistry as Xe FIB can performdelayering on a sub-14 nm technology microprocessor and discusses the differences between the two use cases. Xe Plasma vs. Gallium FIB Delayering Sharang Sharang, Paul Anzalone, and Jozef Vincenc Obona edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS Recent Advances in VLSI Characterization using the TEM Frieder H. Baumann A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS AUGUST 2019 | VOLUME 21 | ISSUE 3 16 26 4 8

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ABOUT THE COVER Writing in a Moonlit Wonderland. Excessive strain during field oxidation created Si defects, causing diode leakage. b = ±a[111]/3 for the nanometer-size stacking fault (SF). (004)-DFTEM revealed the SF fringes and bounding disloca- tions. With g = ( − 220), the fringes and dislocations along [ − 110] were rendered invisible (oval inset). Can you find the nano-tablet? Photo by Wentao Qin, ON Semiconductor, First PlaceWinner in False Color Images, 2018 EDFAS Photo Contest. Author Guidelines Author guidelines and a sample article are available at edfas.org. Potential authors should consult the guidelines for useful informa- tion prior to manuscript preparation.

For the digital edition, log in to edfas.org, click on the “News/Magazines” tab, and select “EDFA Magazine.”

44 TRAINING CALENDAR Rose Ring 48 LITERATURE REVIEW Mike Bruce 48 IN MEMORIAM 50 UNIVERSITY HIGHLIGHT Norhayati Soin, et al.

51 IRPS WRAP-UP David Burgess 54 GUEST COLUMN Tejinder Gandhi 56 ADVERTISERS INDEX

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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 3 2 PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Felix Beaudoin Editor/GlobalFoundries; felix.beaudoin@ globalfoundries.com Scott D. Henry Publisher Mary Anne Fleming Manager, Technical Journals Kelly Sukol Production Supervisor Joanne Miller Managing Editor ASSOCIATE EDITORS Nicholas Antoniou Nova Measuring Instruments Navid Asadi AUGUST 2019 | VOLUME 21 | ISSUE 3 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS

GUEST EDITORIAL

EXPLORATION OF QUANTUM ELECTRONICS AND MAGNETICS FOR BEYOND CMOS COMPUTING Ian A. Young, Intel Corp. ian.young@intel.com

As the keynote speaker at ISTFA 2019, Dr. Young will elaborate on this topic during his presentation on Tuesday, November 12, at 9 a.m. T he unprecedented success of information technology over the past 50 yearswas based onMoore’s Lawand primarily one underlying technol- ogy—complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs). However, along with the slowdown in the rate of power supply voltage reductionwith the end of the CMOS FET’s Dennard scaling era, the power density of the CPU and GPU integrated circuit has been increasing and now challenges today’s power delivery and thermal cooling solutions. Present researchon logic technologies nowaims to complement CMOS rather than completely replace it. This approach is also planned as a continuation of Moore’s Law, which still persists despite multiple claims to the contrary. The beyond-CMOS research effort has been underway for 10 years, funded in the U.S. in large part by Semiconductor Research Corp. In Europe and Asia, recent R&D has resulted in breakthroughs in spin-orbit effects and new approaches to problems such as how to use non-volatile devices and their impact on architecture. The expectation in the research community 10 years ago was that

University of Florida Guillaume Bascoul CNES France Michael R. Bruce Consultant David L. Burgess Accelerated Analysis Jiann Min Chin Advanced Micro Devices Singapore Edward I. Cole, Jr. Sandia National Labs Szu Huat Goh GlobalFoundries Singapore Martin Keim Mentor, A Siemens Business Ted Kolasa Northrop Grumman Innovation Systems

Rose M. Ring Lam Research

t h i s f i e l d wou l d produce a compu- ting technology that surpasses CMOS in almost everyway. The reality is that despite many impres s i ve proposals and dem- onstrations, none of them beats CMOS. However, some of these alternative technologies offer valuable features such as low energy

Sam Subramanian NXP Semiconductors Paiboon Tangyunyong Sandia National Labs David P. Vallett PeakSource Analytical LLC Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr.

Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, designbyj.com

PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is pub- lished quarterly by ASM International ® , 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org.Copyright©2019byASMInternational.Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $150 U.S. per year. Authorizationtophotocopy itemsfor internalorpersonaluse, orthe internalorpersonaluseofspecificclients, isgrantedby ASM Internationalfor librariesandotherusersregisteredwith theCopyrightClearanceCenter(CCC)TransactionalReporting Service, provided that the base fee of $19 per article is paid directlytoCCC,222RosewoodDrive,Danvers,MA01923,USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest.

Courtesy of D.E. Nikonov and I.A. Young: JXCDC, 2015.

operation and non-volatility. Thus, the current vision is that beyond-CMOS circuits will replace CMOS in certain types of computing applications. These new circuits would bemonolithically integratedwith CMOS on the same chip or packaged together in a multi-chip module.

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Xe PLASMA VS. GALLIUM FIB DELAYERING Sharang Sharang, Tescan Brno, s.r.o., Czech Republic Paul Anzalone, Tescan USA Inc., Warrendale, Pennsylvania Jozef Vincenc Obona, Tescan Orsay Holding a.s., Czech Republic

INTRODUCTION Layer-by-layer deprocessing is becoming increasingly vital and challenging for industrial and research applica- tions such as failure analysis, chip reverse engineering, and patent violation detection. Gallium focused ion beam (Ga FIB) and Xe FIB instruments are the go-to tools for chip material analysis in the semiconductor industry for applications like transmission electronmicroscopy (TEM) lamella preparation, circuit edit, and cross-sectional analysis. A common technique for delayering is mechani- cal polishing, which is not precise or localized enough in removing sensitive layers on IC chips. [1,3] Previously these researchers have used a Xe FIB successfully for delayer- ing on sub-14 nm technology from metal 8 to transistor contacts in combination with special gas chemistry. [4] This article shows that a Ga FIB with the same chemistry as the Xe FIB can also performdelayering on a sub-14 nm technologymicroprocessor and discusses the differences between the two use cases. EXPERIMENT DETAILS AND RESULTS Top-down delayering of sub-14 nm technology nodes was performed with both Ga and Xe FIBs using A-Maze special gas precursor (proprietary gas chemistry of Tescan Orsay Holding a.s.). Figure 1a shows a 100 × 100 µm² area opened on sub-14 nm using Xe FIB by aligning the sample analytical working distance to the SEMpositioned orthogonal to the FIB beam. A GIS was inserted to inject A-Maze gas onto the area of interest. Suitable current density and beam shape were used to conduce planar- ity in the presence of the gas chemistry. The process was monitored using end point detection based on the SE signal being generated during the etching process (Fig. 3). The end pointing recognizes peaks as the metal layer and troughs as the via layer, which gives full control to theoperator to start and stop theprocess onany layer of interest. Fine polishing is performed once a specific layer is reached to get rid of residual metal/dielectric from the previous removed layer. Figure 2a shows a 20 × 20 µm²

Fig. 1a Delayeredwindowwith Xe FIB to transistor contacts.

Fig. 1b Nanoprobes performing electrical measurement on a PMOS.

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(a) Fig. 2 (a) Delayered box showing the edge effect and final planarity. (b) Detailed image of the transistor layer. (b)

block of area opened using Ga FIB. Figure 2b displays the details of via contacts uncovered, illustrating final planar- ity and accessibility to the layer architecture for pattern recognition and detection of spyware circuitry. CONCLUSIONS In this article, the extended capability of a Ga FIB with special gas chemistry is demonstrated by performing delayering on an Intel 14 nm chip. Ga FIB or Xe FIB with A-Maze or Nanoflat gas-based assisted etching (FIB-GAE) can remove dissimilar materials with similar removal rates. This produces final roughness of the exposed area under 10 nmRMS for the overall topography. Themethod delivers significant advantages in terms of localized, pre- cise, and layer-by-layer removal alongwithconstantmoni- toring using the acquiredSE signal for endpoint detection.

The process is capable of performing delayering for 10-12 layers on sub-20 nmprocess nodes. The usual size of the area exposedwith delayering can be as large as 20 µm and can be achieved in about 12 minutes. This enhances the workflow capability by enabling yet another applica- tion for a Ga FIB and making it a “must-have” tool in the semiconductor industry for physical failure analysis and cyber-security applications. Gallium implantation in exposed layers is a known drawback, which hinders most electrical characteriza- tion techniques. This is where Xe FIB can be of assistance and can help prepare larger delayered areas (M8 to TCL, size up to 200 µmedge length in under 30minutes), offer- ing access to a wider area range to perform nanoprob- ing (Fig. 1b) and TEM lamella preparation for further analysis.

Fig. 3 Typical end point detection (EPD) generated to help monitor and control layer removal—each peak is a metal layer and each trough is recognized as a via layer.

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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 3 6 ACKNOWLEDGMENTS ABOUT THE AUTHORS

2. Conf. Proc., 2014. 3. R. Alvis, et al.: “Plasma FIB DualBeam: Delayering for Atomic Force NanoProbing of 14 nm FinFET Devices in an SRAM Array,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2015, p 388-400. 4. J.V. Oboňa, et al.: “Delayering14 nm Node Technology IC with Xe Plasma FIB,” European Microscopy Congress, 2016, p 267-268. 5. Conf. Proc., 2016. 6. V. Viswanathan, S. Sharang, et al.: “Precision Xe Plasma FIBDelayer- ing for Physical Failure Analysis of Sub-20 nm Microprocessor Devices,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2017, p 574-599.

The authors would like to acknowledge funding sup- port fromthe Technological Agency of the Czech Republic *TE 01020233 (AmiSpec) and also Brenda Prenitzer, Ph.D., from Nanospective, Orlando, Fla., for providing 14 nm technology samples for the delayering process. REFERENCES 1. P. Carleson, et al.: “Delayering on Advanced Process Technologies using FIB,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2014, p 430-435.

Sharang Sharang is an applications development engineer at Tescan Brno, Czech Republic, spe- cializing in XePlasma FIBapplications. He has beenworking in the fieldof electron and ionoptics since 2013 and specializes in focused ion beam-based semiconductor applications specifically for physical failure analysis. He has a master’s degree in scientific instrumentation from University of Applied Sciences Jena, Germany, focusing on scanning electron microscopy and micro and nano-analysis techniques. He has contributed to several conference papers, articles, and posters. He represents Tescan Orsay Holding across the globe in semiconductor failure analysis conferences and meetings, contributing with leading edge solutions. He is working on a large area deprocessing technique with

special gas chemistries using FIB-SEM systems. He currently works and lives in Brno, Czech Republic. Paul Anzalone works at Tescan in the U.S. as the technical support manager for sales, applica- tions, and service. He has been working in the field of electron and ion optics since 1995. He has published numerous white papers, articles, and posters. He also co-authored two books. Anzalone works closely with strategic customers in the U.S. on delayering techniques with gas chemistries using FIB-SEM systems to expose trojans in semiconductor devices. He is active in cybersecurity detection and analysis using FIB-SEMdelayering techniques. He currently resides inNewHampshire. Jozef Vincenc Oboňa is a product marketing director at Tescan Orsay

Holding, a.s. His primary focus is on theproper positioningandmarketingof Tescan’s FIB-SEMportfolio in the semiconductor market segment and searching for new product development opportunities. He earned a degree in chemistry at the Slovak University of Technology in Bratislava and a Ph.D. in electrical engineering at the Slovak Academy of Sciences. After seven years of postdoctoral positions at universities in Spain and the Netherlands, he started his career as the R&D application manager at Tescan in 2014.

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LARGE AREA AUTOMATED DEPROCESSING OF INTEGRATED CIRCUITS: PRESENT AND FUTURE E.L. Principe, 1 Z.E. Russell, 2 S.T. DiDona, 2 M. Therezien, 2 B.W. Kempshall, 1 K. E. Scammon, 3 and J.J. Hagen 3 1 Synchrotron Research Inc., Melbourne Beach, Florida 2 Ion Innovations, Atlanta 3 PanoScientific LLC, Cocoa, Florida eprincipe@synchres.com

INTRODUCTION Previous research has demonstrated the fundamental workflows to achieve large area automated deprocessing of integrated circuits (ICs). [1-2] This article reviews recent achievements and discusses present limitations of this type of deprocessing. It also describes future integrated circuit deprocessing tool development related topurpose- built laboratory-based hardware and synchrotron-based instrumentation. The emphasis here is on hardware, hardware configurations, and both hyperspectral and rapid image data acquisition methods. Processes related to data reduction to net list are not covered in this article. CURRENT STATE OF LARGE AREA IC DEPROCESSING

imagesacquiredfromadeprocessedsmart card isshown in Fig. 1. Each pFIB delayering operation requires approxi- mately sevenminutesper layer,whileeach imagemontage operation takes approximately 20 minutes per layer. A novel form of tomography was created during this process, distinguished by the fact that it involves a rela- tively large planar x-y area (800 × 800 µm) integrated over a relatively shallow Z depth (~3.0 µm) in 100 nm steps. An example of output from the automated deprocessing routine is shown in Fig. 2. Key elements to the success of the automated delayering process include ultra-thinning of the die from the backside prior to pFIB delayering and the ability to program the operation of the pFIB, SEM, detectors, and stage using custom Python code. Ultra- thinning from the backside to within 1-2 µm of the active layer of the die allows access to the densest features of the

Currently, the most efficient integrated method demonstrated to delayer a multi- layer IC device employs custom instrument automation of gas-assisted etching (GAE) with plasma focused ion beam (pFIB) delay- ering, sequenced with automated scanning electronmicroscope (SEM)montage imaging and conducted on a full die that is ultra- thinned from the backside. [1,2] This robust process has been demonstrated to auto- matically perform the delayering operation on multiple layers unattended and uninter- rupted for a period of up to five days before being manually terminated. The process incorporates the option to acquire images at multiple voltages and with various detec- tors. Apair of backscatter secondary electron

Fig. 1 Example of image output from the auto delayering routine of a smart card. A 5-kV BSE image is shown (left) paired with a 30-kV BSE image (right). The 30-kVdatapeers two to three layers into the circuit, allowing forward modeling of density at depth. Data was acquired from the Florida Institute for Cybersecurity (FICS) Research, University of Florida.

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IC at the outset of the delayering process. This ensures the SEM imaging is of the highest qualitywithminimal surface topography at the layers, which require the highest image resolution. In addition, this workflow allows for electri- cal testing and interrogation of a “live” device. The fact that the ultra-thinning is also an automated, feedback- controlled precision process permits optimal integration into the overall workflow. The ability to independently program the operation of the pFIB, SEM, detectors, and stage using Python (or any preferred language) via an open application programmer interface (API) cannot be overstated. Further, when the programmable instrument control is coupled through an independent computational engine, it creates a bidirec- tional communication interface toenablecomputationally guided microscopy (CGM). After this interface is estab- lished, it is possible to fetch images as they become avail- able and perform near real-time data validation as well as standard operations for distortion correction, stitching, andmontage display. More importantly, the bidirectional communication enables feedback to implement adaptive scanning strategies, compressed sensing, or adaptive ion dwell time at the pixel level to track and correct surface roughening. A computational engine running Dragonfly from Object Research Systems (ORS) as the image pro- cessing and 3D visualization enginewas employed for this article’s research. Figure 3 shows the autodelayering setup and control interface linking Dragonfly to the FIB-SEM.

The degree of open instrument control enabled through an API varies widely depending on the instru- ment vendor. However, vendors are being compelled to provide more complete and open APIs due to end-user pressure driven by opportunities in CGM. Users would be wise to negotiate the type and extent of API capabilities with vendors during an instrument purchase. While the automated deprocessing of ICs described above repre- sents the state of the art, there are several requirements that drive the need for improvements. The main desired enhancements are related to increased data acquisition speed and larger area. The next few sections describe potential methods to increase speed and expand area coverage with laboratory-based instruments as well as synchrotron-based instruments. THE ‘IMAGING PROBLEM’ Next is an examination of the “imaging problem” and the limitations associated with traditional scanning elec- tron imaging. It is assumed that any optimal deprocessing workflow begins with ultra-thinning from the backside of the die. For the sake of this discussion, it is also assumed

ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 3

Fig. 2 Automated plasma FIB tomography created through the automated delayering process (five layers). Integrated circuit is from a smart card chip. Data shown was generated at FICS Research. The chip was ultra-thinned from the backside prior to pFIB delayering using the Varioscale VarioMill. Tomographic data was processed using Dragonfly by ORS.

Fig. 3 The automated delayering user interface couples communication and feedback between the compu- tational engine and the FIB-SEM to permit CGM.

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that a total of five layers would require destructive GAE ion delayering from the backside. The imaging time represents the most significant barrier to increasing the overall speed of IC deprocessing. Consider a dwell time of 1.5 µs and individual image tiles composed of 4096 × 4096 pixelswith a 100 µm 2 field of view (FOV), yielding a 24.4 nm pixel size: It would require 2.9 days to image one layer of a 1 cm 2 die. A 10 nm pixel size would require a 40 µm FOV and an imaging time per layer of 18 days, not including overhead or image overlap. Given those assumptions, total electron imaging time using a traditional SEM could require more than 90 days. The world’s fastest scanning electron microscope, a Zeiss MultiSEM, employs up to 91 simultaneous beams to drive that imaging time down to an impressive three hours. However, that technology comes at a seven-figure cost and does not integrate with a delayering process, along with other pragmatic challenges that will not be discussed here. Next is an exploration of methods used to reduce electron imaging time, other than multi-beam scanning technology, which is covered in later sections. COMPRESSED SENSING WITH POINT SPREAD FUNCTION DECONVOLUTION The same computational engine used to automate the delayering-imaging instrument is designed to implement other advancedCGMmethods suchas compressedsensing (CS) and point spread function deconvolution (PSFD). The implementation of CS in electron microscopy requires a very specific scan generator. Synchrotron Research Inc. has designed a CS scan generator for this purpose, which is coupled to CUDA programmable graphical processing units (GPUs) for CS reconstruction. Figure 4 shows a CS reconstruction and sequential blind PSFD on a synthetic sensing mask from an Intel Skylake 14 nm processor. Denoising and image sharpening are evident, but blind deconvolution is less accurate than fromameasured PSF, which is a functionof anarray of systemconditions. In fact, a complete PSF characterization of an SEM or FIB (which

can be automated) reveals the transmission function of the microscope and captures systemic and temporal deviations, therefore doubling as a health monitoring system. The application of PSFD is particularly useful in order to obtain optimal resolution at low voltage and higher currents. An automated deprocessing instrument incorporating compressed sensing could reduce imaging time by as much as fivefold, reducing the deprocessing time of five layers to approximately 18 days. This approach assumes that the upper layers would be more effectively deprocessed using methods other than destructive ion delayering and electron imaging. One such possibility, synchrotron-based tomography, will be discussed further in an upcoming issue of EDFA. Commercial pFIB-SEM instruments are not optimized for IC deprocessing because they were never designed with such a specific purpose in mind. A typical FIB-SEM is designed to be a highly versatile platform to accom- modate a wide range of applications. If an instrument configuration is designed with deprocessing of ICs as a primary objective, the geometry and functionality may be better adapted, and the software and controls better streamlined for the purpose. In addition, surface sensitive ion and electron spectrometers with small form factors have recently been developed, which add considerable analytical value atmodest cost. The elemental and chemi- cal information is extremely valuable to complete the characterizationof the device, while the surface sensitivity establishes nanometer scale end point detection (EPD). The efficiency of these small spectrometers can be quite high, especially if their design is tuned to the applica- tion. Figure 5 shows an overview of a working instrument design by the authors for an advanced IC deprocessing tool currently being developed in collaboration with interested parties. Referencewill bemade to this platform and accompanying figures while exploring and discussing functionalities desired in a dedicated IC deprocessing DEDICATED AUTOMATED IC DEPROCESSING HARDWARE

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(b)

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Fig. 4 (a) Intel Skylake 14 nm processor‒original image. (b) Synthetic sensing mask of (a) with 20% of the scan data. (c) Reconstructed image and PSFD applied to scan data in panel (b).

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arrangement. Several elements of the hardware and instrument controls are based on prior experience with components used in synchrotron-based instrumentation. The platform is intended to be ultra-high vacuumcompat- ible, but may also operate in the vacuum range typical for commercial electron and ion microscope platforms. The automated sample handling can accommodate several backside-loaded die along the vertical length of the sample carrier frame channel. Apreviously proven transfer design is used to capture the backloaded die into platens, which then insert into the vertical sample manipulator channel. Themanipulator allows precision x-y-z-rmotion. The sample may be rotated to face normal to any probe and the x-y translation can be used to control working distance with respect to any probe or set of probes. This vertical sample carrier channel was originally conceived to permit routing for cryogenic cooling of biological samples dispersed onto a silicon wafer. The overreaching concept of the platformaddressed is to combine a BIB and FIB into a common workflow to permit a range of resolution and scale to the physical delayering process. Rapid improve- ments in the affordability, reliability, and reduced form factor of femtosecond laser sources make them a very attractive addition to theworkstation. The augmentation of a new generation of compact ion and electron spec- trometers add yet another new dimension of elemental and chemical analysis to the data cube, while acquiring signals currently being ignored during the process. The sample handling is designed to easily accommodate multiple die for extended runs with a simple, reliable, and programmable range of motion. These represent some of the attractive features and functions of a dedicated IC deprocessing instrument. The instrument control platform for the proposed dedicated IC deprocessing instrument is based on the Experimental Physics Industrial Control System (EPICS) (https://en.wikipedia.org/wiki/EPICS). EPICS is an open

ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 3

Fig. 5 Isoview of PIE.

instrument. The tool is configured to allow modification and probing using photons, ions, and electrons (PIE) in one instrument platform. As depicted in Fig. 6, there are various modes of processing and data collection. In Mode 1, a broad ion beam (BIB) and SEM imaging is coin- cident. In Mode 2, a pFIB and SEM imaging is coincident. InMode 3, the pFIB and imaging secondary ionmass spec- troscopy (SIMS) are at optimal coincidence. In Mode 4, a femtosecond laser is oriented normal to the sample surface. A “standard” gas injection system (GIS) and in- chamber electron detectors (not shown) are orientated out of the horizontal plane. The compact Auger electron spectroscopy (AES) detector is also located out of the horizontal plane and may be operated concurrently with the SEM column. The configuration is based on actual available hardware components with accurate form factors. Note that the primary probes are arranged in the horizontal plane, with various detectors and accessories above thehorizontal planewitha vertical samplehandling

Fig. 6 PIE platformdepicting primary deprocessing and analysismodes. Mode 1: Configuration for BIBmilling andSEM imaging. Mode 2: Configuration for pFIB delayering and SEM imaging. Mode 3: Configuration optimal for pFIB-SIMS imaging. Mode 4: Configuration for nonthermal bulk ablation.

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not become gas-starved. A single standard GIS needle proximal within ~150 µm of the surface will not evenly distribute an etch gas across an entire die, therefore alter- nativesmust be sought. An alternative could take the form of multiple GIS needles directed onto the die, incorpora- tion of a gas-concentrator shield, or even allowing the entire chamber environment to back-fill with the desired gas chemistry. All such options have specific advantages and disadvantages. Ideally, the best scenario provides an option formultiple gas chemistries and the ability to regu- late specific ratios of chemical species depending on the metal composition and density. In theworking design, the alternative of embedding the plumbing for the gas chem- istries into the sample carrier frame is considered. The gas chemistries can be manifolded and dispersed within the frames surrounding the four sides of the slightly recessed back-loaded die. This is another approach to achieving sufficiently uniform and concentrated gas chemistry at the near surface of the full die. ION SOURCE ALTERNATIVES A pFIB is not technically required to perform auto- mated IC deprocessing. However, it does provide a superior method to precisely open well-defined areas on the micron scale. Other source gases are also possible in a pFIB, such as argon, oxygen, nitrogen, helium, and sulfur hexafluoride. While these alternative gases have an inferior milling rate compared to Xe, they provide varying aspect ratios, or in the case of species like O and SF 6 , deliver active chemistry for secondary ion yield enhance- ment or chemical etching. Therefore, thepFIB is apowerful component of a comprehensive deprocessing tool. But in many ways, a BIB source ismore efficient over large areas and more economical in terms of capital expense to address the generic delayering of a full die. A BIB can effectively cover an entire diewith variable spot size and scanning options. It can also be configured for Xe, Ar, and other gases. While a BIB has lower brightness than a pFIB, that is not themost critical parameter when considering large area deprocess- ing. The SEM in this platform concept is located between the BIB and pFIB so that imaging may be performed when using either ion source. COMPACT SIMS INSTRUMENTATION A pFIB is a required ion source when ion delay- ering is conducted in combination with imaging SIMS, which allows simultaneous collection of secondary ions generated during the GAE ion

source set of network-based software tools and applica- tions, which provide a software infrastructure for use in building distributed control systems commonly used around the world in synchrotron facilities and particle accelerators. Using an EPICS backbone allows integration ofwell-establishedmethodswhile creatingauniformstan- dard for instrument control thatmaybeopenlydeveloped. GAS ASSISTED ETCHING Regardless of the ion source, an effective gas chemistry is critical to enable ion-based delayering, and gas chemis- tries are available for pFIB-SEMdelayering. In general, the goal of the gas chemistry in conjunctionwith appropriate ion beamenergy and current density is to homogenize the material removal of very heterogeneous structures con- sisting of varyingmetal density (i.e., copper and tungsten) and interlayer dielectric comprised of porous silicon. To achieve this, the gas chemistry is designed to impede the rate of the faster milling components in order to balance the process. Gas chemistry may be modulated depend- ing on the metal density in the region of interest. In the specific case of gallium FIB delayering, the gas chemistry also plays the critical role of minimizing redeposition by volatilizing sputtered species. Indeed, while galliummay be used effectively for delayering with an appropriate delayering gas, the fact that gallium is not inert makes it a less desirable source. Without a suitable gas chemistry, the interaction between redeposited gallium and copper can be extremely problematic. This issue is demonstrated in Fig. 7, which shows the “pooling” of gallium-copper interphases surrounding the etch area. Moreover, when considering very large area deprocessing on the scale of an entire die, it is important to ensure the surface does

Fig. 7 Interaction of Ga and Cu without gas-assisted etch chemistry. Left panel shows Ga EDS map is overlaid onto the SEM image, enclosing the region where the gallium FIB was etched in a 400 µm 2 area from the backside on an Opteron die. Right is a higher magnification composite SEM-EDS image taken from the area outlined in the left panel red box. Data shown was collected at FICS Research using a Bruker EDS.

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delayering process. While most of the sputtered material is in the form of neutrals, the yielded ions may be captured and analyzed to add elemental surface composition. If post-ionization methods are applied (i.e., laser post-ionization), the yield is further enhanced. SIMS hyperspectral data may in turn be combined and interleaved with SEM imaging data using data fusion methods. As a surface analytical technique, the SIMS functions as a sensitive EPD scheme tomonitor delayeringprog- ress and uniformity. The compact SIMS shown in Fig. 8a is the design of Ion Innovations andutilizes a novelminiaturizedadaptationof a classicmagnetic sectormass spectrograph. Thismass spectrograph incorporates compressive sensing techniques (spatially coded apertures) and stigmatic lens designs to maintain high resolving power and sensitivity for its size. [3-4] Dual polarity (not simultaneous) and single polar- ity designs are available and offer simultaneous acquisi- tion of the full mass spectra within a specified range. [5] COMPACT AES INSTRUMENTATION Analogous to the benefits of SIMS while conduct- ing GAE ion delaying, AES contributes complementary analytical information concurrent with SEM image data acquisition. In addition to the type I, II, and III secondary and backscatter electrons being induced, Auger electrons are also being induced by the primary electron beamwith a yield inversely proportional to the x-ray yield. Thus, AES is very attractive for light elements, including lithium. AES provides not only elemental information, but also chemi- cal signatures for many compounds used in ICs, such as nitrides and silicides. In addition, the surface sensitivity means that AES is also good for EPD. Similar to the SIMS hyperspectral data, AES hyperspectral data may also be integrated using data fusion methods. The compact AES detector envelope shown in Fig. 8(b) is a prototype devel- opment of PanoScientific LLC and may also be operated in an x-ray photoelectron spectroscopy mode. FEMTOSECOND LASER The femtosecond laser shown in the hardware model serves a dual purpose: It may be applied for nonthermal ablation directly, or for post-ionization during the SIMS data collection. There is also the potential for laser-medi- ated chemical etching. Together, the extremely short pulse laser and variable pulse laser are a powerful component of any deprocessing tool. CONCLUSIONS An API with a customgraphical user interface has been applied to link a computational engine for instrument

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control, data collection, and data visualization with bidirectional communication to a pFIB-SEM platform to achieve automated and unattended IC deprocessing (delayering) on a full die ultra-thinned from the back- side. This instrument control link forms the basis for the much broader andmore general methods of CGM. Such a platform facilitates the rapid development of functional- ity outside the resource limits and priorities of original equipment instrument vendors. This article describes advances for future laboratory- based instrumentation dedicated to IC deprocessing using a CGM platform. Applications include CS and PSFD moduleswithmachine learning toenhancedata collection speed and resolution. A “PIE” instrument configuration for IC deprocessing is proposed, which incorporates several processing modalities and analytical data collection modes beyond what is currently employed. A future article will highlight the application of synchrotron chemical imaging and x-ray tomographic methods to integrate with the deprocessing workflow. This workflowwould blend electron-based imaging from the backside with synchrotron-based x-ray tomographic methods to complete the reconstruction. REFERENCES 1. E.L. Principe, et al.: “Plasma FIB Deprocessing of Integrated Circuits from the Backside,” Electronic Device Failure Analysis, 2017, 19 (4), p. 36-43. 2. E.L. Principe, et al.: “Steps Toward Automated Deprocessing of Integrated Circuits,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2017. 3. Z.E. Russell:: “Coded ApertureMagnetic Sector Mass Spectrometry,” Dissertation, Duke University, 2015. [Online.] Available: http://hdl. handle.net/10161/11396. 4. Z.E. Russell, S.T. DiDona, J.J. Amsden, et al.: J. Am. Soc. Mass Spectrom, 2016, 27 (4), p. 578-584. 5. U.S. Patent No. WO2017075470A1, 2015,. Washington: U.S. Patent and Trademark Office. Fig. 8 (a) Compact SIMS instrument designed by Ion Innovations for elementalmappingandendpoint detectionduring thedelayering process. (b) Compact AES in development by PanoScientific LLC, showing selected electron trajectories. Overall length is 300mm. (a) (b)

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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 3 14 ABOUT THE AUTHORS

EdwardL. Principe obtainedaPh.D. in engineering science fromThePennsylvania StateUniversity and M.S. and B.S. degrees in mechanical engineering from the University of Central Florida. He is founder and president of Synchrotron Research Inc., a designer andmanufacturer of imaging NEXAFS tools. Principe has authored two textbook chapters on FIB-Auger and FIB-based 3Dnanotomographic reconstruction and co-authored the EDFAS Best Paper in 2013 and EDFAS Outstanding Paper in 2017. He holds two patents in FIB-based 3D reconstruction and is focused on the development of compu- tational guided microscopy.

Zachary E. Russell earned his B.S. degree in applied physics with honors fromAppalachian State University, Boone, N.C., and his Ph.D. in electrical and computer engineering from Duke University, Durham, N.C. He completedhis postdoctoral research fellowship at theGinzton Laboratory of Stanford University, Calif. Russell is the founder and director of R&D at Ion Innovations, and is working on research in metrology, instrumentation design and miniaturization, electron and ion source design, machine learning and computer vision, and related computational simulation and optimization techniques.

Jeffery J. Hagen received his undergraduate degree in chemistry from Hamline University, St. Paul, Minn., and his Ph.D. in analytical chemistry from the University of California, Riverside. He is co-founder and managing director of PanoScientific LLC, driving development of compact electron spectrometers. He is also principal at Hagen Scientific leading the development of firmware and soft- ware controls for medical devices, test systems, and analytical instrumentation. Previously, Hagen was a software developer for Physical Electronics (Eden Prairie, Minn.) and Charles Evans & Associates (now Evans Analytical Group, EAG).

KirkM. Scammon earned hisM.S. inmechanical engineering fromtheUniversity of Central Florida in 1996, where he studied corrosion and environmentally induced cracking of nickel-base superal- loys. He is co-founder and managing director of PanoScientific LLC, involved in the development of compact electron spectrometers. He is also a research engineer at the University of Central Florida, working primarilywith electron spectroscopy and electronmicroscopy. Scammon has participated in the development of two imagingNEXAFS spectrometers for the NIST beamline at NSLS-II, Brookhaven National Laboratory. Brian W. Kempshall earned a B.S. in mechanical engineering and Ph.D. in

materials science and engineering from the University of Central Florida. He has co-authored over 20 refereed journal articles and conference proceedings. Kempshall is co-founder of Nanospective, a materials characterization company with over 14 years of experience in intellectual property asser- tion, competitive intelligence, reverse engineering, and failure analysis in the semiconductor, laser, optical, biological, polymeric, and geological materials industries. He is also co-founder of an analyti- cal instrument development company andworks with synchrotron instrumentation at national labs.

Shane T. DiDona received dual B.S. degrees in chemical engineering and physics and an M.S. degree in chemical engineering from North Carolina State University, Raleigh, in 2011 and 2012, respectively. Presently, he is pursuing a Ph.D. with the Nanomaterials and Thin Films Laboratory, Duke University, Durham, N.C. His current research interests include computational charged particle lens design, instrumentation design, computer-aided design, simulation, computer vision, machine learning, and optimization. He is also co-founder and lead programmer at Ion Innovations, Atlanta. MathieuTherezien receivedM.S. degrees in engineering, physics, and chemis-

try fromESPCI (Paris) in 2000, environmental sciences fromEPFL (Lausanne, Switzerland) in 2001, and forestry fromDuke University (Durham, N.C.) in 2008. He earned a Ph.D. in environmental engineering from Duke University in 2016. His research projects introduced novel visualization and simulation tools to the field of tree physiology. He joined the Ion Innovations team in 2017 as a research scientist where he works in the fields of machine learning, optimization, and computer vision.

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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 3 16 EDFAAO (2019) 3:16-24

1537-0755/$19.00 ©ASM International ®

FAILURE ANALYSIS FOR HARDWARE ASSURANCE AND SECURITY M. Tanjidur Rahman and Navid Asadizanjani Department of Electrical and Computer Engineering, University of Florida, Gainesville nasadi@ufl.edu

analysis, fault injection techniques, and side-channel analysis have been developed to support chip failure analysis (FA) at the post-silicon stage. Access to the physi- cal chip aswell as several FA analysis tools like chippolish- ing, microscopy, probing, focused ion beam (FIB), x-ray imaging, and laser voltage probing are required for the inspectionmethods namedabove. In recent years, FA tools used for physical inspection have experienced significant advancement in facilitating defect localization. Demand for higher yield and faster FA and fault localization at smaller technology nodes also catalyzed the progress and revolution in FA techniques and tools. However, an adver- sary can use these same FA methods and tools to attack a chip and compromise security by exposing assets like sensitive information, intellectual property, firmware, and cryptographic keys. Physical attackmethods are capable of compromising the confidentiality and integrityprovided by modern cryptography and security measures through observation of a chip’s silicon implementation. Methods developed for the economic growth of the semiconduc- tor industry now appear as tools to gain access to assets hidden in modern embedded devices. Identifying assets worth protecting, developing effective countermeasures against physical attacks, and implementing physical inspection methods as trust

INTRODUCTION Embeddeddevices and internet of things (IoT) technol- ogy have become an indispensable part of modern life. Such advancement in IoT devices requires a state-of-the- art fabrication process. Accordingly, the semiconductor industry has evolved toward a horizontal businessmodel. However, the involvement of third party intellectual property (IP) owners and offshore foundries has raised concerns regarding security and trust. Outsourcing design and fabrication invites vulnerability regarding malicious activities and alterations in integrated circuits (ICs). Becausehardwaregenerates a trustedand secureenviron- ment for privileged software, it is considered the root of trust for any systemon chip (SoC). The entire root of trust is violated if any malicious alteration is detected. Such malicious modification to the structure and function of a chip can be identified as a hardware trojan. Researchers have proposed several electrical-basedmethodologies to detect these types of modifications. However, in recent years, the research community has proposed physical inspection methodologies as an emerging solution to verify and assess the root of trust. Physical inspectionmethods such as reverse engineer- ing, electrical and optical probing, photonic emission

Fig. 1 Taxonomy of physical inspection/attacks.

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verification techniques requires a discerning look into the inspection/attackmethodologies. Therefore, a taxonomy (Fig. 1) of physical inspection/attacks is presented based on sample preparation and the nature of the inspection/ attacks process. Physical inspection/attacks can be per- formed noninvasively, semi-invasively, or invasively. In the past, when compared to noninvasive attacks, inva- sive and semi-invasive attacks were considered a lesser threat to security due to the requirement of equipment, expertise, and execution time. But in recent years, even though new features have been added, FA equipment is becoming cheaper and more accessible. Further, FIB and scanning electron microscopy (SEM) imaging systems are available inmany academic/industry labs and can be rented for only a fewhundred dollars per hour. Therefore, a surge in physical attacks is expected in the near future. Equally important, growth is also anticipated in physi- cal inspection-based techniques to provide an effective means of security and trust verification. NONINVASIVE PHYSICAL INSPECTION/ ATTACK METHODS A noninvasive inspection/attack attempts to extract assets without tampering with the packaging or struc- ture of the chip/printed circuit board (PCB). Noninvasive attacks are executed actively or passively. Examples of active noninvasive attacks are fault injection techniques, brute force, and data remanence. Fault injection inspec- tion/attack involvesmanipulating a chip in order to cause a transient fault in an operational chip to evaluate the fault-tolerance of the device. An adversary can use fault injection to bypass the security condition check. Brute force attack is amethodological application of a large key set to extract the exact cryptomodule key. Passive attacks like side-channel analysis have been studied extensively for exposing cryptographic keys or sensitive information. In addition, side-channel signal analysis using transient and quiescent power, delay, and electromagnetic ema- nation has been widely proposed for trust verification against trojans. [1-2] INVASIVE PHYSICAL INSPECTION/ ATTACK METHODS Invasive attacks require access to the internal compo- nents of a chip or PCB. Hence, depackaging and decap- sulation are two common initial steps taken to prepare a sample. Invasive inspection/attacks leave tamper evi- dence in the chip due to the application of processes like plasma/wet etching or FIB. A successful invasive attack requires an expensive toolset like anSEM, FIBworkstation,

microprobing station, high-resolutionopticalmicroscope, plasma etcher, polisher, or simple chemical lab. Prevalent forms of invasive inspection/attacks include reverse engi- neering, electrical probing, and circuit edit. REVERSE ENGINEERING Reverse engineering of an IC involves analyzing the in- ternal structure, connection for extracting design, stored information, and functionality of the chip. Subsystem- level reverse engineering is comprisedof structural and in- formationextraction (Fig. 1). ChipandPCB reverse engineer- ing are common forms of structural reverse engineering. Full-blown chip reverse engineering is comprised of five steps. 1) Decapsulation: Exposes the internal die, lead frame, and die connecting components (bond wire and ball grid arrays). Decapsulation can be completed from front side or backside. 2) Delayering: Process of removing materials layer by layer for imaging and analysis. Wet/dry plasma etching, FIB, or polishing are used for delayering the chip. 3) Imaging: After exposing a new layer, high-resolution images are collected and stitched together for extract- ing netlists. Commonly, an optical microscope or SEM is used for imaging. In recent years, x-ray synchrotron and ptychography have been used to extract circuit connec- tion information from a 14 nm node IC, nondestructiv- ely. [3] The technique is often referred to as nondestructive. However, because the samples for this type of imaging need to be as small as a few tens of microns, it is actually a destructive technique. 4) Annotation: All image features such as the active region, gates, capacitors, inductors, resistors, vias, con- tacts, andmetal lines are annotatedmanually or by using image processing software. 5) Netlist and functionality extraction: Different compo- nents of the circuit layout are identified and the intercon- nection between components is obtained to fully extract the netlist. Figure 2 shows the steps and deprocessing/ analysis methods used in chip reverse engineering. PCB reverseengineering focuseson identifyingall com- ponents on the board and the interconnection between them. PCB reverse engineering can be destructive or non- destructive. In a destructivemethod, delayering, removal of components, and imaging are performed iteratively, layer by layer. X-ray tomography is used for noninvasive imaging and extracting the internal structure of a PCB. [4] Later, the internal structure is analyzed to extract the PCB circuit connection diagram.

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