August_EDFA_Digital

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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 3

(a) Fig. 2 (a) Delayered box showing the edge effect and final planarity. (b) Detailed image of the transistor layer. (b)

block of area opened using Ga FIB. Figure 2b displays the details of via contacts uncovered, illustrating final planar- ity and accessibility to the layer architecture for pattern recognition and detection of spyware circuitry. CONCLUSIONS In this article, the extended capability of a Ga FIB with special gas chemistry is demonstrated by performing delayering on an Intel 14 nm chip. Ga FIB or Xe FIB with A-Maze or Nanoflat gas-based assisted etching (FIB-GAE) can remove dissimilar materials with similar removal rates. This produces final roughness of the exposed area under 10 nmRMS for the overall topography. Themethod delivers significant advantages in terms of localized, pre- cise, and layer-by-layer removal alongwithconstantmoni- toring using the acquiredSE signal for endpoint detection.

The process is capable of performing delayering for 10-12 layers on sub-20 nmprocess nodes. The usual size of the area exposedwith delayering can be as large as 20 µm and can be achieved in about 12 minutes. This enhances the workflow capability by enabling yet another applica- tion for a Ga FIB and making it a “must-have” tool in the semiconductor industry for physical failure analysis and cyber-security applications. Gallium implantation in exposed layers is a known drawback, which hinders most electrical characteriza- tion techniques. This is where Xe FIB can be of assistance and can help prepare larger delayered areas (M8 to TCL, size up to 200 µmedge length in under 30minutes), offer- ing access to a wider area range to perform nanoprob- ing (Fig. 1b) and TEM lamella preparation for further analysis.

Fig. 3 Typical end point detection (EPD) generated to help monitor and control layer removal—each peak is a metal layer and each trough is recognized as a via layer.

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