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reliability solutions in critical applications including aero- space, avionics, and automotive. As a result, the group developed a comprehensive framework that eliminates the effect of aging degradation. The framework starts at the device level by modeling the effect of aging degrada- tion for 16-nm FinFET technology, and concludes at the circuit level by proposing circuit level techniques that mitigate the effect of aging for 16-nmFinFET circuits. The group is currently conductingmodeling and experimental characterization of graphene FETS, in collaboration with LJMU and MIMOS. In addition, novel techniques for assessing the reli- abilitymechanisms of devices were developed by looking at negative bias temperature instability (NBTI), [9-10] hot carrier injections (HCI), and probing of energy distribution of positive charges in gate dielectrics and its application to lifetime prediction. [11] REFERENCES 1. R. Gao, et al.: “NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling,” IEEE Trans. Electron Devices, 2017, 64 (10), p 4011-4017. 2. R. Gao, et al.: “Reliable Time Exponents for Long TermPrediction of Negative Bias Temperature Instability by Extrapolation,” IEEE Trans.

Electron Devices, 2017, 64 (4), p 1467-1473. 3. R. Gao, et al.: “A Discharge-Based Pulse Technique for Probing the EnergyDistributionof Positive Charges inGateDielectric,” IEEE Trans. Semicond. Manuf., 2015, 28 (3), p 221-226. 4. L.-Y. Ma, et al.: “A Novel Design of a Low-voltage Low-loss T-match RF-MEMS Capacitive Switch,” Microsyst. Technol., 2018, 24 (1), p 561-574. 5. C. Fearday, et al.: “Development of an Inductor Incorporated onto a Carbon Fiber MAV Structural Component,” Microsyst. Technol. , 2017, 23 (5), p 1433-1442. 6. N.A.F. Othman, et al.: “Optimization of 7 nm Strained Germanium FinFETDesignParameters using Taguchi Method andPareto Analysis of Variance,” ECS J. Solid State SC, 2018, 7 (4), p 161-169. 7. N.A.F. Othman, et al.: “Impact of Channel, Stress-RelaxedBuffer, and S/D Si 1− x Ge x Stressor on the Performance of 7-nm FinFET CMOS Design with the Implementation of Stress Engineering,” J. Electron. Mater., 2018, 47 (4) p 2337-2347. 8. F.A.M. Rezali, et al.: “Performance and Device Design Based on Geometry and Process Considerations for 14/16-nm Strained FinFETs,” IEEE Trans. Electron Devices, 2016, 63 (3) p 974-981. 9. Y.A. Wahab, et al.: “Defects Evolution Involving Interface Dispersion Approaches in High-k/metal-gate Deep-submicron CMOS,” Microelectron. Reliab., 2014, 54 (9-10) p 2334-2338. 10. H. Hussin, N. Soin, et al.: “Effects of Gate Stack Structural andProcess Defectivity on High-Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs,” Sci. World J., 2014. 11. S.W.M. Hatta, et al.: “Energy Distribution of Positive Charges in Gate Dielectric: Probing Technique and Impacts of Different Defects,” IEEE Trans. Electron Devices, 2013, 60 (5) p 1745-1753.

ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 3

IRPS WRAP-UP

INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM 2019 David Burgess, Accelerated Analysis davidburgess@acceleratedanalysis.com T he 2019 International Reliability Physics Symposium (IRPS) was held at the Hyatt Regency inMonterey, Calif., March 31 to April 4. The conference was well attended

by more than 400 participants from the U.S., Europe, Asia, and other regions of the world. IRPS was co-located with the International ESD Workshop (IEW). Participants from both events shared a Poster Reception including ESD research from IEW as well as 74 IRPS poster papers. The symposium began with two days of tutorials covering introductory andadvanced reliabilityphysics topics. More than 100 platformpresentations addressed failuremechanisms and

The picturesque Hyatt Regency Monterey housed this year’s IRPS event.

testing considerations of semiconductor devices and microelectronic systems. At the same time, equipment and service exhibitors were located adjacent to presentation rooms. Exhibit representatives were kept busy meeting with attendees and answering equipment related questions. Despite the long days, the Tuesday evening workshops fueled by pizza and beer were productive and well attended. The IRPS conference is sponsored by the IEEE Reliability Society and IEEE Electron Devices Society. The 2020 event will be held March 29 to April 2 in Dallas.

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