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Figure 1.
integrates the 3D engine so that the
user never has to learn the intricacies
of a full-wave-solver environment.
Structure geometries are passed,
EM ports are formed, simulations
are run, and S-parameter results are
returned and incorporated into time-
domain simulations, automatically.
Recently,
PCB
power-delivery
systems have come under stress.
What formerly were “power
planes” are now collections of
highly compromised power “areas,”
(Figure 1) whose integrity must be
simulated. HyperLynx has added
multiple engines - two 2.5D solvers,
the industry’s fastest DC/IR-drop
simulator, and a fast quasi-static 3D
solver - to enable a full set of power-
integrity features, all of which are
available side-by-side in the same
application as HyperLynx signal-
integrity capabilities. This version
adds a second, more-advanced 2.5D
solver, capable of not only pure
power but also mixed signal-and-
power modeling, which can be used
to add accuracy to SI simulations
when simultaneous-switching-noise
(SSN) complications are suspected.
Analysis from Beginning
to ENd
Simulating every detail of signal
routing and power delivery on a PCB is
powerful, but possibly overwhelming.
The HyperLynx DDRx batch-
simulation wizard pioneered easy
setup,
automated
whole-bus
simulation, and consolidated results
reporting for memory interfaces.
Now, HyperLynx extends this popular
capability to DDR4 and LPDDR4
interfaces. HTML-based reporting
creates design documentation
and allows internal Web-based
“publication” of results (Figure 2).
A new analysis tool has become
popular for SERDES busses. This
tool, called Channel Operating
Margin (COM) allows checking the
“goodness” of links based on a
specific, complex set of simulation
steps that in the end produces a single
pass/fail number per-channel (Figure
3). The new version of HyperLynx
offers the first robust commercial
implementation of COM for 100GbE
signaling, with all simulation details
fully automated.
Another way to streamline the
daunting task of simulating all signal
and power effects on a large PCB
is to proactively identify portions of
a design that most need detailed
analysis, and to reduce the time
required for simulation by promoting
aggressive re-use of expensive-
to-create models (like 3D-based S
parameters).
This is accomplished by integrating
the powerful HyperLynx DRC engine
directly inside the HyperLynx SI/PI
environment. Now the super-fast DRC
engine (capable of scanning board-
wide for routing and other geometric
anomalies in seconds) can provide
“simulation triage,” by accurately
finding layout structures that violate
design intent or best practice. For
example, HyperLynx SI/PI deploys
this engine to automatically find
all differential via pairs that do not
conform to pre-designed known-
good “patterns”; and to group all
such vias into sets for which only
one 3D-EM S-parameter extraction
(automatically run) is needed per
set, saving potentially many hours of
simulation time per board.
Continuing with ease-of-use and fast
interactive analysis, the new release
puts dual emphasis on a very different
type of usage: in a pure batch-mode
environment, driven by scripts, run on
entire layouts at least once-per-day,
with little/no user intervention and
a completely suppressed GUI. Much
investment has gone into robusting
HyperLynx for such use: the ability to
efficiently handle very large layouts
(including extra-deep stackups,
huge net counts, and entire multi-
22 l New-Tech Magazine Europe