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Cypress Unveils PSoC 6, the Industry’s Lowest

Power, Most Flexible MCU Architecture, Setting a

New Standard for Battery-powered, Secure IoT

Devices

Game-changing MCU Architecture Delivers a Dual-Core

Processing Platform that Seamlessly Integrates Critical,

Hardware-Based Security and Connectivity for the IoT

EMBEDDEDWORLD,NUREMBERG,CypressSemiconductor

Corp. (NASDAQ: CY) today announced PSoC® 6, its newest

microcontroller (MCU) architecture that is purpose-built for the

Internet of Things (IoT). The architecture is built on ultra-low-

power 40-nm process technology and delivers the industry’s

lowest power and most flexible solution, with integrated

security features required for next-generation IoT devices.

The architecture fills a gap in the IoT solution space between

power-hungry and higher-cost application processors and

performance-challenged, single-core MCUs. The dual-core

ARM® Cortex®-M4 and Cortex®-M0+ architecture lets

designers optimize for power and performance simultaneously.

PSoC 6 enables engineers to uniquely create innovative,

next-generation IoT devices leveraging the unique PSoC

fabric with its easy-to-use, software-defined peripherals. More

information on the PSoC 6 MCU architecture and access to

the PSoC 6 Early Adopter Community is available at http://

www.cypress.com/PSoC6.

“As the leader in wireless solutions for the IoT, we saw first-

hand that our customers need a better processing solution that

balances performance and power, while implementing critical

security functions for connected devices,” said Hassane El-

Khoury, President and CEO at Cypress. “Our PSoC 6 MCU

architecture is purpose-built to solve these problems, marking

a significant addition to our broad embedded systems solution

portfolio for the IoT.”

Setting a New, Industry-leading, Ultra-Low-Power Benchmark

Cypress’ proprietary ultra-low-power 40-nm SONOS process

technology enables the PSoC 6 MCU architecture to feature

industry-leading power consumption with 22 µA/MHz and

15 µA/MHz of active power on the ARM Cortex-M4 and

Cortex-M0+ cores, respectively. With dynamic voltage and

frequency scaling (DVFS), the PSoC 6 MCU architecture offers

both performance- and power-critical processing capability.

The dual-core architecture enables power-optimized system

design where the auxiliary core can be used as an offload

engine for power efficiency, allowing the main core to sleep.

Raising the Bar for IoT Security with a Trusted Solution

The PSoC 6 MCU architecture provides a hardware-

based Trusted Execution Environment (TEE) with secure

boot capability and integrated secure data storage to

protect firmware, applications and secure assets such as

cryptographic keys. PSoC 6 implements a broad set of

industry-standard symmetric and asymmetric cryptographic

algorithms, including Elliptical-Curve Cryptography (ECC),

Advanced Encryption Standard (AES), and Secure Hash

Algorithms (SHA 1,2,3) in an integrated hardware coprocessor

designed to offload compute-intensive tasks. The architecture

supports multiple, simultaneous secure environments without

the need for external memories or secure elements, and

offers scalable secure memory for multiple, independent user-

defined security policies.

“Every connected device represents a potential network

vulnerability. With billions of potential vulnerabilities, security

is paramount and the need to design in security at the lowest

level in an IoT device is more important than ever,” said John

Weil, vice president of the MCU Business Unit at Cypress. “We

built PSoC 6 to enable our customers to protect their products

from cyber-attacks while at the same time empowering them

to create new, innovative IoT devices leveraging the flexible

and easy-to-use PSoC architecture.”

Enabling New, Innovative IoT Devices with Intuitive Software

Support

Offering best-in-class flexibility and ease-of-use, the PSoC 6

MCU architecture can serve as the catalyst for differentiated,

visionary IoT devices. Software-defined peripherals can

be used to create custom analog front-ends (AFEs) or

digital interfaces for innovative system components such as

electronic-ink displays. The architecture offers flexible wireless

connectivity options, including fully integrated Bluetooth Low

Energy (BLE) 5.0. The PSoC 6 MCU architecture features the

New-Tech Magazine Europe l 79