Previous Page  78 / 84 Next Page
Information
Show Menu
Previous Page 78 / 84 Next Page
Page Background

new products

78 l New-Tech Magazine

New Cadence Modus Test

Solution Delivers Up to 3X

Reduction in SoC Test Time

Physically aware 2D Elastic

Compression architecture reduces

test logic wirelength by up to 2.6X

and enables compression ratios

to scale beyond 400X without

impacting design size

Cadence Design Systems, Inc.

(NASDAQ: CDNS) todayannounced

the new Modus™ Test Solution

that enables design engineers to

achieve an up to 3X reduction in test

time, thereby reducing production

test cost and increasing silicon

profit margins. This next-generation

test solution incorporates patent-

pending, physically aware 2D

Elastic Compression architecture

that enables compression ratios

beyond 400X without impacting

design size or routing.

To address the challenges that come

with testing designs, the Cadence®

Modus Test Solution includes the

following innovative capabilities:

2D compression: Scan compression

logic forms a physically aware

two-dimensional

grid

across

the chip floorplan, enabling

higher compression ratios with

reduced wirelength. At 100X

compression ratios, wirelength for

2D compression can be up to 2.6X

smaller than current industry scan

compression architectures.

Elastic compression: Registers

embedded in the decompression

logic enable fault coverage to be

maintained at compression ratios

beyond 400X by controlling care

bits sequentially across multiple

scan cycles during automatic test

pattern generation (ATPG).

Embedded memory bus support:

A shared test access bus can

be inserted to perform at-speed

programmable memory built-in

self test (PMBIST) across multiple

embedded memories in an IP

core. New soft programmable test

algorithms for FinFET SRAMs and

automotive safety applications are

also included with this feature.

Powerful common scripting and

debug environment: Design for test

(DFT) logic insertion and ATPG

capabilities use a new, unified Tcl

scripting and debug environment

that is shared with the Cadence

Genus™ Synthesis Solution, the

Innovus™ Implementation System

and the Tempus™ Timing Signoff

Solution.

“Our next-generation Modus Test

Solution delivers new, innovative

patent-pending technology that

fundamentally changes the way

design and test engineers address

the test problem,” said Dr. Anirudh

Devgan, senior vice president and

general manager of the Digital and

Signoff Group at Cadence. “By using

a physically aware approach in a

2D grid, and compressing patterns

sequentially as well, the Modus Test

Solution can significantly reduce

digital test time in comparison to

traditional approaches, thereby

giving Cadence customers yet

another significant profitability

advantage.”

For more information on the Modus

Test Solution, please visit www.

cadence.com/news/modus.

Samsung Launches New

LED Module Lineup, inFlux,

for High-Flux Industrial

Lighting

Samsung Electronics, a world

leader in advanced components,

introduced inFlux, a new lineup

of high-flux (extremely bright),

linear LED modules optimized

for industrial lighting applications

such as plants, parking lots and

warehouses. The LED modules

serve as a replacement for

conventional T8 and T5HO (high

output) tubes and are suitable for

high-flux LED luminaires covering

up to 40,000lm (luminous flux*).

“By providing a wide variety of

installation layout options and

brightness intensities, our new

inFlux linear module will deliver

greater design flexibility and

convenience for lighting designers,

as well as high performance and

reliability for fixture manufacturers,”

said Jaewook Kwon, Vice President,

Lighting Marketing Group, LED

Business

Team,

Samsung

Electronics. “We will continue to

reinforce our well-differentiated LED

lighting engine lineups to be able to

meet more diverse market needs.”

The Samsung inFlux LED module

incorporates the company’s mid-

power LED package (LM301A),

which features advanced “flip chip”

technology that enables a shorter

junction-to-base distance and

less thermal barrier layers in each

package, while avoiding the need

for metal wire bonding. This leads

to lowering the thermal resistance

of the packages, and permits each

package to handle a wide range of

current with improved light efficacy.