New-Tech Europe Magazine | May 2018

any desired location, answering the basic expectation of any designer to realize unique and secured CMOS chips. This via patterning integration on production wafers shows the latest achievements obtained on the Mapper FLX-1200 platform, while demonstrating its compatibility with standard optical lithography and its capability to be transparently inserted into standard CMOS integration flow. This technology maturity, therefore, moves from the level of proof of concept to the pre-production level. To further the platform’s maturity, Mapper and Leti will pursue intensifying the tool hardening. They will also extend the overall demonstration program to highlight and value the capability of this technology to fully meet industry needs and expectations. This activity of cyber-security, one of CEA Tech’s key expertise areas, is actively developed, as it represents a clear technology path for the manufacturing of tomorrow’s devices. Furthermore, the FLX-1200 platform installed in Leti’s silicon pilot line is also now accessible for private customer patterning demonstrations. (please contact authors: laurent. pain@cea.fr, isabelle.servin@cea.fr) Notes [1] I. Servin et al., Proc. SPIE 10584, 1058411 (2018)

Figure 3. Pattering demonstration on first customer 300 mm wafer exposed with FLX-1200 multi beam tool at 5kV (Via layer node 40nm CMOS)

FLX-1200 platform, which enables mix-and-match operations with conventional optical lithography. The collaboration also developed a complete integration process flow. Final technical results are compliant with industrial specifications for the N40 dual-damascene process flow. This achievement confirms that Mapper’s technology can be qualified for IC CMOS 40nm-node logic, including specific process steps (Figure 3): Wafer clamping on silicon wafer, including metallic deposit layers Customer design transfer on the machine without execution errors Reading alignment marks created with standard optical scanner Alignment on the buried layer and exposing the layout of real products. This successful demo is promising for Mapper, as it demonstrates compliance with the CMOS manufacturing standard. It also shows the ability to write on- demand specific circuit structures at

and the N40 logic cell inside the field with via features designed at 63nm. Each block size represented an area 3x3mm². Leti has developed a lithographic stack containing standard industrial materials, as used today for optical scanners. The e-beam resists are chemically amplified type resists. The lithographic performances and etch transfer results were fine-tuned on customer wafers to fit the N40 specification targets in terms of CD control, CD uniformity and pattern fidelity. Specific circuit structures on demand The fruitful partnership between Leti and Mapper produced a unique competence-and-technical combination for data preparation, proximity-effect corrections, tool monitoring, metrology and etch- transfer processes. Matching strategy with standard optical scanner is now operational and qualified thanks to the optical- alignment system installed inside the

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