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Figure 2- Detailed Diagram of ATE and SSR
Figure 1- Overall Architecture of ATE to test SSR
parameters. Functionality tests
included target simulator to the
radar at 1,090 MHz, video signal
detection, and radar scan converter
display using synthetic transistor-
transistor logic (TTL) video signal
and LAN communication. Reply
pulses in the target and multitarget
simulators were stationary and
trajectory motion. Figure 1 illustrates
the overall architecture of the ATE
connected to SSR.
System Overview
We created a system composed of
an NI PXI-1042 eight-slot chassis
and an NI PXI-8196 embedded
controller. We kept the radar either in
transmitting mode or receiving mode
to test the Tx and Rx functionality.
External antenna signals north and
azimuth count pulses (ACPs) were
generated and simulated through
an FPGA board. Target reply pulses
were generated through an NI PXI-
5671 vector signal generator (VSG)
at 1,090 MHz. The system acquired
demodulated video signals from the
receiver through an oscilloscope
card for Rx functionality tests. High-
power transmitted RF pulses were
acquired through an NI PXI-5661
vector signal analyzer (VSA) to
measure Tx signal power and pulse
parameters. The synthesized video
at the TTL level generated from the
radar processing unit was acquired
through FPGA digital input and used
for a radar scan converter to display
the target on a polar plot with its
range and azimuth position, info
code, altitude, and country code.
Figure 2 shows a detailed diagram
of the ATE connected to SSR.
Each trigger and sync pulse was
synchronized with the interrogating
RF pulse of the SSR. To protect the
instruments, we switched off the
transmitter of the radar during the
Rx tests because the radar had a
built-in TR module. Both Tx and Rx
ports shared the same physical port,
which connected to an antenna.
The VSA and VSG connected to
this same physical port, replacing
52 l New-Tech Magazine Europe