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Figure 1 - reVISION Stack
developers
use
Xilinx®
All
Programmable System on Chip (SoC)
and Multi Processor System on Chip
(MPSoC) devices from the Zynq®-
7000 and Zynq® UltraScale™+
MPSoC families to implement their
solution. These devices provide high
performance processors closely
coupled with programmable logic,
allowing the Embedded Vision
developer to optimize their solution.
The use of Zynq SoC or Zynq
UltraScale+ MPSoC devices enable
the developer to benefit from the
any-to-any connectivity which comes
with the use of programmable logic.
This programmable logic can also
implement the image processing
pipeline(s), providing a performance
increase due to its parallel nature.
Using the programmable logic
increases the system performance,
connectivity and the performance per
watt of power dissipated providing a
more efficient solution overall.
The processing cores can be used for
higher level application functionality,
such as decision making based
on the provided information and
communication between systems and
with the cloud.
To address the security concerns
which come with autonomous and
remote applications, both device
families provide a secure environment
with support for encrypted secure boot
and ARM® Trust Zone technology
within the processor, and the ability to
implement anti tamper functionality.
Using
Zynq-7000
and
Zynq
UltraScale+
MPSoC
devices
provide significant capability to
the Embedded Vision developers
allowing the challenges and trends
to be addressed. Leveraging these
capabilities requires a development
ecosystem that enables the Embedded
Vision developer to utilize not only the
benefits of using these devices, but
also provide the ability to still use the
commonly used frameworks within their
solution. This is where the reVISION™
Stack comes in.
reVISION Stack
The reVISION Stack was developed to
enable Embedded Vision developers
to address the four key challenges
identified above, which are evident
within the embedded vision sphere.
These challenges can be summarized
as responsivity, reconfigurability,
connectivity and software defined.
To address these four driving trends,
the reVISION Stack combines a
wide range of resources enabling
platform, application and algorithm
development. As such, the stack is
aligned into three distinct levels:
1.
Platform layer. This is the lowest
level of the stack and is the one on
which the remaining layers of the
stack are built. As such it provides
both a hardware definition of the
configuration of the Zynq-7000 / Zynq
UltraScale+ MPSoC and the software
definition via a customized operating
system to support the hardware
definition. This hardware definition
can define the configuration of either
a development or production ready
board such as a System on Module.
It is within the hardware definition
that the sensor and system interfaces
are defined. The hardware platform
will be captured using Vivado® HLX,
and may leverage IP blocks from both
Xilinx and third party suppliers along
with the use of high level synthesis
to create specialist IP. This layer will
also provide software drivers for IP
modules and an updated PetaLinux
configuration if required, to support
the software defined environment at
the higher level.
2.
The middle level of the stack
is called the algorithm layer.
Development at this level takes place
within the eclipse based SDSoC™
environment. SDSoC is a system
optimizing compiler which allows
development using a software defined
environment. Crucially as we develop
our software algorithms, bottlenecks
in performance can be identified and
removed by accelerating functions
into the programmable logic. To the
user this process is seamless, using a
combination of High Level Synthesis
and a connectivity framework to
move a function from executing in
software to implementation in the
programmable logic. It is at this
level OpenCV is used to implement
the image processing algorithms for
the application at hand. To reduce
identified bottlenecks within the
image processing algorithm, reVISION
provides a wide range of acceleration
ready OpenCV functions. Support is
also provided at this level for the most
common neural network libraries,
including
AlexNet,
GoogLeNet,
SqueezeNet, SSD, and FCN.
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