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In part one of this series, we talked
about the role of the hardware
designer, specifically comparing the
ideal version of the hardware designer
with the real-world version. From the
emails I received, this is a bittersweet
reality for many readers of this blog.
Today, we will revisit the life of a
hardware designer whose company,
like most of the leading semiconductor
companies, is using a hardware design
paradigm that puts more focus on the
real design engineering work by doing
that design work at a higher level of
abstraction.
What are these companies
doing differently?
In short, these companies allow (and
expect!) their designers to perform
high quality design work, as compared
to spending their time coding up
one RTL implementation that may
or may not be the most efficient
implementation.
Their hardware designers create
designs at a higher level of abstraction,
using languages such as SystemC and
C++, then use an automated high-
level synthesis (HLS) tool to translate,
or more correctly synthesize, this to
RTL for implementation on an ASIC
or FPGA. The RTL can be pushed
through the rest of the IC tool chain
automatically.
This allows the designers to focus
on functionality and high-level
architecture in their high-level design.
From that design, the HLS tool creates
one or more RTL implementations
optimized toward the constraints
specified by the designer.
Their designers make quantitative
trade-offs,
evaluating
multiple
implementations to find the one that
best meets the requirements of the
current project. Better still, the same
high-level design, commonly termed
“behavioral IP,” can be used for other
projects even if the design constraints
are vastly different.
But instead of getting on my soapbox to
espouse the values of HLS, let’s focus
on the more important question…
What drove these
companies to use an HLS-
based flow?
Of course, the motivations are slightly
different for each company, but there
are some common themes.
A) In order to move up the
value chain, large SoC companies
are providing more tailored and
differentiated offerings than ever
before. In the traditional hardware
design flow, this means design teams
find themselves buried in a never
ending stream of “exactly same as last
one, but…” requirements. They have
found that HLS provides a much more
efficient way to produce so-called
“derivative designs,” because design
code of behavioral IP does not have
to be rewritten from scratch for each
derivative, even if the functionality
changes significantly.
B) Smaller companies, or small
teams within larger companies, have
found that HLS provides a way for
the small teams to be much more
Making Hardware Design Great Again in 2017
- Part Deux
Dave Pursley, Cadence
Chip Design
Special Edition
62 l New-Tech Magazine Europe