wiredInUSA - August 2012
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industry in January. The OEM-specified
cable is manufactured as solid conductor,
stranded conductor or multiples of each
from as small as a 0.5mm outer diameter
to a 1.2mm outer diameter, with other sizes
available on request.
The blasting cables are insulated in polyvinyl
chloride, high-density polyethylene or
halogen-free insulations, meeting the
safety requirements of the South African
mining industry, says sales and marketing
manager Peter Willers, adding that Walro
Flex has already manufactured and sold a
significant volume of blasting cable to the
local industry.
Walro Flex began manufacturing the
double-insulated welding cable in May.
The cable uses dual insulation materials,
with the outer layer meeting the SANS 1576
welding cable specification. It can be
used for low-voltage, flexible power cable
applications, as well as standard duty
welding applications in the mining, panel
building and industrial sectors.
The cable has been SABS-approved and
is manufactured to the SANS 1574-3
specification, with a voltage rating of 600/
1,000V. Walro Flex’s cable manufacturing
facility consists of four main process
divisions – the rod breaking and wire
drawing, the extrusion, the stranding and
bunching, and the highly flexible, superfine
conductor departments.
Manufacturer claims sub-20nm breakthrough
The problem of creating copper
interconnects in sub-20nm chips has been
resolved, according to semiconductor
manufacturing specialist Applied Materials.
The company, an equipment maker for
the semiconductor, flat panel display and
photovoltaic markets, has developed a
new manufacturing technique which it
claims will enable chipmakers to build
interconnects far smaller than the current
20nm limit.
Announced at the Semicon West event
in July, Applied Materials’ Endura Amber
system promises to shrink copper intercon-
nects in semiconductors to 10nm or less.
A modern semiconductor can contain
over 60 linear miles of copper wiring across
as many as 10 billion vertical connections
- and more will be demanded as process
sizes shrink, and increasing features are
added to chips.