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ʷʬʧ ʭʥʩlz ʤʸʨʬʠ ʬʹ 10 ʤ ʸʥʣʤ ʺʥʧʴʹʮ
ʤʩʶʦʩʮʩʨʴʥʠʡ ʺʥʰʩʩʴʥʠʮ ʬʨʰʩʠ ʺʸʡʧʮ
ʺʮʸʡ ʯʤʥ ʸʥʶʩʤ ʺʩʩʢʥʬʥʰlzʨ ʺʮʸʡ ʯʤ ʤʠʬʮ
ʹʮʺʹʮʬ ʸʹʴʠʬ ʮ ʲ ʺʠʦʥ ʤʸʥʨʷʨʩlzʸʠʤ
ʭʥʮʩʱʷʮʥ ʤʤʥʡʢ ʺʩʺlzʸʲʮ ʤʩʶʸʢʨʰʩʠ
ʤlzʥʮʰ ʷʴʱʤ ʺlzʩʸʶ ʬʲ ʤʸʩʮʹ lsʥʺ ʭʩʲʥʶʩʡ
Stratix 10, ʺʠ ʺʥʬʬʥlz 10 ʤ ʸʥʣʤ ʺʥʧʴʹʮ
.Arria 10 MAX 10
ʤ ʺʧʴʹʮ ʬʹ ʺʥʰʥʹʤ ʺʥʸʦʢʰʤ
ʬʹ ʨʡʩʤʡ lsʸʣ ʺʥʶʸʥʴ ʺʥʬʥlzʩ ʺʥʲʩʶʮ ʤʸʨʬʠ ʬʨʰʩʠ ʬʹ SOC ʥ Stratix 10 FPGAs
ʺʥʰʥʸʺʩ ʺʥʷʩʰʲʮʤ ʺʥʬʥlzʩ ʺʩʺlzʸʲʮ ʤʩʶʸʢʨʰʩʠʥ ʺʥʴʩʴʶ ʷʴʱʤ ʺlzʩʸʶʡ ʺʥʬʩʲʩ ʭʩʲʥʶʩʡ
ʭʩʺʰlzʺʮʤ ʭʩʡʩlzʸʤ ʷʥʹʡ ʺʥʸʧʺ ʠʬʬ
ʭʩʸʹʴʠʮ ʬʨʰʩʠ ʬʹ 14nm Tri-Gate ʺʩʢʥʬʥʰlzʨʡ ʸʥʶʩʩʥ HyperFlex ʤ ʺʸʥʨʷʨʩlzʸʠ
.70% ʩʣlz ʣʲ ʤlzʥʮʰʤ ʷʴʱʤ ʺlzʩʸʶʥ ʺʥʮʣʥʷ ʺʥʧʴʹʮʮ 2 ʩʴ ʨʲʮlz ʬʹ ʸʣʺ ʩʲʥʶʩʡ
ʯʥʰlzʺ ʩʸʢʺʠʬ ʤʰʲʮlz ʩʣʥʧʩʩ ʯʴʥʠʡ Stratix 10 ʤ ʺʠ ʺʥʡʶʮʮ ʥʬʠ ʭʩʣʷʺ ʺʥʸʱʧ ʺʥʬʥlzʩ
ʺʩʥʥʷ ʺʸʥʹʷʺ ʬʬʥlz ʤʶʷʤ ʩʷʥʥʹ ʩʮʥʧʺ ʬlzʬ ʠʡʤ ʸʥʣʤʮ ʭʩʲʥʶʩʡ ʩʸʩʺʲ ʺʥlzʸʲʮ ʬʹ
ʥlzʥ ʤʣʩʣʮ ʤʷʩʣʡ ʩʠʥʴʸ ʸʥʣʩʹ ʩʠʡʶ ʯʥʱʧʠ ʡʥʹʧʩʮ ʺʩʨʥʧʬʠʥ
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