Previous Page  50 / 84 Next Page
Information
Show Menu
Previous Page 50 / 84 Next Page
Page Background

50 l New-Tech Magazine Europe

ith the rise of the Internet

of Things and Big Data

processing, the need for transferring

and processing data has skyrocketed,

and CPUs alone can no longer address

the exponential increase. Adding

more processors and more virtual

machines to run a given application

just doesn’t cut it, as there is only

so much that can be parallelized on

multiple CPUs for a given application.

Field-programmable gate arrays, on

the other hand, have the requisite

I/O bandwidth and processing power,

not only from a pure processing

standpoint but, equally important,

from a power standpoint. For data-

center equipment manufacturers,

the use of FPGAs has long been an

appealing prospect. Intel’s recent

acquisition of the second-largest

FPGA vendor is further testament that

a CPU-only solution no longer suffices.

The major roadblock to more-

widespread FPGA adoption has been

the complexity of implementing them.

Until now, the only way to develop

an application on an FPGA-based

platform has been to deal with some

of the lowest levels of hardware

implementation. This has kept a large

potential customer base-software

developers-away from the devices and

has made life increasingly complicated

for traditional FPGA designers.

Recent methodologies for FPGA

design, centered on high-level

synthesis (HLS) tools and leveraging

software programming languages

such as OpenCL™, C and C++, have

provided a sandbox for software

developers to reap the benefits of

FPGA-based hardware acceleration

in numerous applications. But the

methodologies often fall short in one

essential respect: enabling software

developers to define and configure, on

their own, the hardware infrastructure

best suited for their application. The

industry has continued to pursue the

holy grail of a high-level workflow for

implementing applications on FPGA-

based platforms that does not require

specific FPGA expertise.

Over the past five years, PLDA has

developed just such a workflow. Called

QuickPlay, it efficiently addresses the

implementation complexity challenge

and enables multiple use models for

FPGA development. But one of its

core sources of value is the way in

which it lets software developers take

applications intended for CPUs and

implement them, partially or fully, on

FPGA hardware. QuickPlay leverages

all of the FPGA resources, turning

these powerful but complex devices

into software-defined platforms that

yield the benefits of FPGAs without

the pain of hardware design.

Consider a software algorithm that can

be broken down into two functions:

W

A Novel Approach to Software-Defined FPGA

Computing

Stephane Monboisset

,

QuickPlay