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result, the challenge is passed on to

the circuit level. Initially to the circuit’s

analog-front-end, and subsequently

to digital signal processors. Available

analog IPs are generic, maybe

programmable to some extent, but

not co-designed with the sensor

and the reference circuits that are

required at system level. As a result,

the traditional analog IP buy-in model

where a set of IPs is glued together

in a chip will result in a sub-optimal

system. Instead of working with

standard component analog IP, a

much better approach is to work with

proven topologies (whose functionality

is already proven in silicon) and fine-

tune them for the application’s sweet

spot.

A last and equally essential aspect

that the new hardware hipsters have

covered is electrostatic discharge

(ESD), electrical overstress (EOS) and

latch-up. Bart Keppens from Sofics

says that what he has learned by

supporting innovative startups is that

many of the applications require non-

standard on-chip ESD/EOS protection

clamps, which are not always covered

in mass-produced designs. “For

example, the driving voltage of the

implanted chip to restore hearing for

(near) deaf people is in the order of

20V, much beyond the typical I/O

interfaces provided by the foundry or

I/O providers. Similarly, small signals

(order of a few mV or mA) captured

by sensors for motion detection and

touch remain hidden in the noise or

are lost due to leakage. Moreover,

the probability of ESD stress is much

higher as they are operated in harsh

environments. For example, the plastic

of your smartphone cover rubbing

on the cloth of your back-pocket

can generate very high voltages just

millimeters away from very sensitive

components, such as high-speed USB

ports.”

Enabling low-cost

prototyping and small-

volume production

For substream innovators, unlike

for larger companies, achieving the

lowest possible unit production cost

is not the first concern. They can

reduce the production unit cost later

on, once the product is on the market

and customers turn out to buy more

products than anticipated. Their

game plan centers on producing truly

innovative and high-margin products

for niche markets, with the potential

to grow into larger, more mature

markets.

Instead, when a startup or an

innovative SME implements an IoT

product involving a custom chip

design, the go/no-go decision is

typically taken by private or venture

capital investors and dominated

by the required amount of upfront

investment (NRE cost), the time-to-

market, and the ability to precisely

define the chip’s requirements.

“That is where IC-link and its design

partners may help,” says Ramses

Valvekens. “They can help lower the

NRE costs and shorten the time to

market through their extensive IP and

know-how. In addition, together with

the customer, they will help define

and focus the chip requirements.”

One essential factor included in

the NRE is the initial cost of the

lithographic mask set needed to

process the wafers. These can cost,

even for mature technologies, in

the range of 100,000s of dollars.

Especially to lower these high

NRE cost for SMEs, foundries have

introduced multi-project wafers

(MPWs) and made these accessible

through partners such as imec IC-

link. In MPWs, designs of many

customers share space on the same

mask, but with hard limits imposed

on the maximum number of chips per

wafer, and the total number of wafers

that can be ordered. For very small

production runs measured in the

thousands, mature MPW technologies

offer extremely low initial costs, as

low as 10,000s of dollars for a batch

of approximately 100 prototypes of

32 mm2. Below figure illustrates the

impact that MPW processing has on

small volume production, as well as

the change in the cost model when

higher production volumes require a

transition to a dedicated mask.

Substream innovation is

here to stay

The convergence of high-growth,

fragmented, wirelessly connected

application domains characterized

by manufacturing sweet spots using

mature technologies has led to an

explosion of activity by SMEs. New

product ideas can be generated by

small teams of people and taken

quickly to small volume production

and are no longer only the domain

of large international corporations.

Imec IC-link and its partners have

committed to support this process, by

providing infrastructure, design and

IP assistance.

23 l New-Tech Magazine Europe