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ring and mixed topologies and they
are not limited to a specific data
rate. Industrial applications will
use 100Mbit and 1Gbit data rates
mainly. Therefore, TSN provides
the convergence between the IT
and OT networks. This convergence
reduces the cost of implementing the
network, significantly lowering the
cost of ownership and operation.
TSN Implementation
Correctly implementing TSN requires
a solution which can provide a low
latency and deterministic response at
TSN end points and TSN bridges. Many
applications solve this challenge by the
combination of a processor and a FPGA
connected together over a high-speed
link such as PCIe. This two-chip solution
not only increases occupied board space,
power consumption, development
time and cost but also prevents a
holistic integrated solution from being
developed. As the design is segmented
between two devices, this also increases
the complexity of verification.
Increasingly, IIoT solutions providers
are using All Programmable Zynq
®
-
7000 and Zynq
®
UltraScale™+
MPSoC devices to implement their
solutions. These devices provide a
combination of Processing System
(PS) and Programmable Logic (PL)
enabling the implementation of
acquisition, control and processing
applications by optimal use of the PS
and PL thanks to:
1.
Ability to interface and control a
wide range of sensors, actuators,
motors and other application-
specific interfaces.
2.
Ability to implement complex
processing at the edge, for
example machine learning, sensor
fusion, image processing and real-
time analytics.
3.
Scalability concerning the number
of network interfaces.
4.
Security and the ability for the
device and system to be secure in
terms of Information Assurance,
Anti-Tamper, and Trust.
The support of any-to-any interfacing
and the ability to couple coupled
Processing Systemand Programmable
Logic makes the Zynq-7000 and Zynq
UltraScale+ MPSoC devices ideal
to implement TSN next to a user
application.
Xilinx's 1G/100M TSN Subsystem
LogiCORE IP consists of FPGA Logic for
MAC, TSN Bridge and TSN Endpoint.
The TSN design with dedicated logic
resources guarantees that the timing
behaviour is strictly deterministic.
Software which runs in the SoC’s
Processing System is for for network
synchronization, initialization, and
for the interfacing with network
configuration controllers for stream
reservation. The software is designed
for running on Petalinux and will be
published for Yocto builds.
The LogiCORE IP also comes with
an optional integrated time-aware
L2 switch that creates the chain or
tree topology that is required in
many industrial applications without
allocating another port at an external
TSN switch. Seamless Redundancy
(P802.1CB) also requires the
additional port. The complete IP is
illustrated in Figure 2, the user can
freely configure before synthesis
whether or not the switch shall be
integrated.
Once instantiated, the TSN IP core
provides individual AXI Streaming
ports for each traffic class. Scheduled
traffic, reserved traffic and best
effort traffic are supported. The
AXI Streaming ports connect to
infrastructure that is introduced by
Xilinx’s Vivado
®
Design Suite. AXI Lite
is used for the configuration of the
TSN blocks.
Xilinx provides a ready-to-use
implementation
for
evaluation
purposes that includes Direct
Memory Access separately for each
of the traffic classes. This evaluation
system can be used as is to test the
behavior between Xilinx components
as well as in combination with 3rd
party equipment or with protocol
analyzers. Figure 4 shows a block
diagram of the evaluation system.
As Programmable Logic is flexible,
it also provides the ability to update
the IP Core as the TSN standards and
Figure 3.
TSN IP in Xilinx Zynq-7000 or Zynq UltraScale+ MPSoC.
28 l New-Tech Magazine Europe