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Figure 4.
TSN implementation for evaluation purposes (here: Zynq
UltraSale+ MPSoC).
Figure 5.
TSN Evaluation System (here: for Zynq UltraScale+ MPSoC).
market segment specific conformance
tests progress, while devices with
fixed hardware implementations
(like custom ASICS and Application
Specific Standard Products - ASSPs)
lack the option to introduce functional
changes along the TSN evolution.
To demonstrate the TSN IP core
in action, Xilinx developed a
demonstration application for both
the ZCU102 and ZC702 development
boards, featuring devices from the
Zynq UltraScale+ MPSoC and Zynq-
7000 families, respectively. When
two of these boards are connected
(Figure 5) it enables network traffic
to be transmitted and received,
enabling validation of TSN networking
capabilities.
To further support TSN deployment
and applications, Xilinx is a member
of the Time Sensitive Networking
testbed at the Industrial Internet
Consortium (IIC). Participation within
this testbed provides the ability
to perform vendor interoperability
testing, along with testing of high
performance and latency critical
applications. This testing can occur
both formally on one of the two
permanent testbeds located in either
the USA or Europe.
Wrapping it up
To enable deployment of the cyber
physical systems for Industrie 4.0 and
IIoT, there needs to be convergence
between IT and OT networks. TSN
provides the ability to converge
these networks, offering significant
advantages in network connectivity,
scalability and cost of deployment
and ownership. Implementing TSN
within an All Programmable Zynq-
7000 or Zynq UltraScale+ MPSoC
device provides the user with a
single chip solution, which can also
provide the processing capability in
the PS and PL to perform the IIoT
application at the edge.
Xilinx’s TSN has been released with
the name 1G/100M TSN Subsystem
LogiCORE IP in May 2017 for early
access customers and will continue
the rollout in Q4/2017.
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