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complex designs begin to suffer
from high Control PLD I/O count and
board congestion.
•
Reduced reliability because
the Power Good fault detection is
inaccurate (typically 8% to 20%
error) and cannot monitor trends in
supply voltage.
•
Adding
Telemetry
(monitoring the actual supply
voltages instead of the Power
Good signal) requires adding an
A/D converter, increases cost &
complexity to the board.
•
Requires a board-level
engineer (with digital expertise) to
implement, someone who, in many
cases, is not be a power supply
expert.
In this split-function architecture,
a Power Manager IC is responsible
for monitoring and sequencing the
board's DC-DC converters (Fig.3).
Because it directly monitors the
supply's voltage the Power Monitor
can also perform trimming and
margining. The Control PLD uses the
supplies' Power Good status lines
to generate the necessary control,
status and housekeeping signals.
For these designs, the Power Manager
functionality is typically defined
using GUI-based configuration tools
while the Control PLD logic is defined
using VHDL or Verilog.
Pros:
•
Lower Control
PLD I/O
count because the Enable function is
handled by the Power Manager.
•
Lower board congestion
means a simpler layout and fewer
board layers.
•
By directly monitoring the
supply voltages, the Power Monitor
IC can get a more accurate picture
of overall system health and enable
higher system reliability.
Cons:
•
Power manager ICs increase
BOM cost – especially if multiple
devices are required.
•
This architecture can provide
Event-Based response but it adds to
design complexity if more than one
Power Manager is employed.
•
Scaling sequencing to more
complex designs can be difficult –
especially if it involves partitioning
functionality across multiple Power
Manager ICs.
•
Since the design process is
Fig.4: A Hardware Management system implemented using a
Control PLD and an MCU
Fig.5: A Hardware Management system implemented using a
Control PLD with an on-chip ADC
Power Architecture #3: Housekeeping using Control PLD with
Microcontroller-based Power Management through a PMBus
Power Architecture #4: Power Management and
Housekeeping using a Control PLD with on-chip ADC
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