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In recent years, the technology of
3D integration has evolved into an
economically interesting road. In
particular, the technology is used
to package the CMOS imagers you
find in your smartphone, the high-
bandwidth DRAM memory stacks
used in high-end com-puting but
also in advanced graphics cards.
3D integration allows a significant
reduction of a system’s footprint,
and enables ever shorter and faster
connections between that system’s
sub-components. Rather than
stacking chips, it is also possible to
rep-artition a 2D systems-on-chip
(2D-SOC) design into circuit blocks,
realized in separate wafers that are
stacked and tightly intercon-nected.
This is called 3D systems-on-chip
(3D-SOC). By clever partitioning of
the circuits, the power-performance-
area can be significantly improved,
providing a path to extend Moore’s
law scaling.
3D systems-on-chip: a clever partition-ing of circuits to
improve area, cost, power and performance
Dr. Mieke Van Bavel
The 3D technology
landscape
The
continued
scaling
of
microelectronic circuits has allowed
the crea-tion of extremely complex
systems-on-chip (SOC). At the same
time, several specific applications
(such as high density memory,
high voltage, analog signaling and
sensors) have driven technology
developments in various directions.
In this complex landscape, on
the one hand, many electronic
systems still consist of a multitude
of components that are packaged
individually and interconnected
using conventional printed circuit
boards. On the other hand, more
advanced 3D integration and
interconnect technologies have
emerged, reducing the size of the
electronic systems, and enabling
faster and shorter connections
between their sub-circuits. These
abilities have made 3D integration
one of the techniques that will
allow the industry to keep pace with
Moore’s Law.
In this 3D technology landscape,
several classes of 3D integration
can be defined. The main difference
between these classes is related
to the level of partitioning, in
other words: at which level in the
interconnect hierarchy the systems
are ‘cut’ into different pieces. Each
of these clas-ses requires different
process schemes and 3D integration
techniques, achieving progressively
smaller contact pitches. A first class
is what we call system-in-a-package
(or SiP), where the partitioning is
done at package level – by stacking
packages on top of each other, or by
inte-grating multiple die in a single
package. Among the technologies
used to realize SiPs are package-to-
package reflow and fan-out wafer
46 l New-Tech Magazine Europe