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Fig 3:
Illustration of 3D-SOC partitioning based on the
scalability of the technologies
Fig 4:
Video illustrating the principle of multicore
processor repartitioning.
(https://vimeo.com/171362602)Fig 5:
From a 2D-SOC (multiple large IP blocks) to a 3D-SOC (IP blocks re-arranged across two chip levels and
further IP block sub-partitioning).
Power, performance,
area and cost benefits
through clever
partitioning
The imec researchers use physical
design tools to find an optimal 3D
functional partitioning of high-
performance systems. A typical
example is a larger SOC which
consists of many cores, L1 memories
associated with these cores and
L2 memory that is shared. This
can be ripped up so that all the
memory is brought to a top die,
and the logic to a bottom die. We
now end up with two dies, half the
size of the original big die. And this
significantly improves the system’s
yield (defined as the percentage
of good dies on a wafer) which
decreases as a function of the
die’s area. In addition to this cost
and area gain, the length of the
wires between the processor and
the memory becomes significantly
shorter after stacking the two dies,
giving additional gain in power
and performance. These gains are
typical for anything that is 3D. But
there is more. For the original 2D die,
the wafer manufacturing process
needs to be optimized for both
logic and memory technologies.
By splitting the die into two dies,
one for logic, one for memory,
the processes can be tuned for
logic and memory separately. And
this will further improve the yield.
Also, logic typically requires a large
number of metal layers (typically
12 to 14), while memory typically
requires fewer layers (5 or 6). This
implies that the wafer containing
the memory part can now be made
relatively cheap – as the back-end-
of-line cost makes up a large part of
the total wafer cost.
In a next step, the partitioning can
be revised by making even smaller
functional IP blocks and rearrange
them into another shape that would
further reduce the wire length. The
(re-)partitioning should however
be done in a clever way, avoiding
over-partitioning. For example, if
a circuit consists of sub-circuits
that are extremely interconnected,
ripping them apart may result in
too many wires that go up and
down between the two resulting
dies. And that would cause more
problems than solving anything. A
clever way of partitioning may for
example be based on the scalability
of the different technologies. While
we keep on scaling transistors
according to Moore’s Law, it gets
more and more difficult to get an
48 l New-Tech Magazine Europe