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Fig 1:
3D stacked IC: processed wafer with chips
stacked on top using a die-to-wafer process.
Fig 2:
Wafer-to-wafer bonding with 1.8 micrometer
pitch overlay accuracy.
level packaging, in combination
with solder balls. Contact pitches of
current solutions are rather coarse,
in the 400 micrometer range. Imec’s
re-search into new approaches to
fan-out wafer level packaging intends
to increase the interconnectivity of
this class of SiP by a factor 100,
target-ing interconnect pitches
of 40 micrometer. The technique
is applied for example for mobile
applications such as smartphones.
In a second class, called 3D stacked
IC or 3D-SIC, the partitioning is done
at die level and individual dies are
stacked on top of each other. 3D-SIC
partitioning is achieved using die-to-
interposer stacking or die-to-wafer
stacking, where finished dies are
bonded on top of a fully processed
wafer. Dies are interconnected using
through-Si vias and microbumps.
In the industry, microbump pitches
down to 40 micrometer are
achieved today. Imec’s research
goal is to bring this pitch down,
well below 20 micrometer, as such
increasing the interconnectivity by
one to two orders of magnitude.
A typical application example is
wide I/O memory, where vertically
stacked DRAM chips (3D-DRAM)
are connected on a Si interposer
together with a logic die and an
optical I/O unit.
3D systems-on-
chip: higher density
through heterogeneous
integration
With advanced CMOS scaling,
new opportunities for 3D chip
integration with even higher
interconnect densities and smaller
pitches arise. Rather than realizing
a SOC as a single chip, it has now
become possible to realize different
functional partitions of a SOC circuit.
Stacking such partitions results in a
so-called 3D system-on-chip. These
are packages in which partitions with
varying functions and technologies
are stacked heterogeneously, with
interconnect densities below 5
micrometer. The system partitioning
can be done at different levels of
the interconnect hierarchy – at the
global wiring level (long wires, cross
chip), intermediate wiring level,
or local wiring level (short wires,
interconnecting e.g. intra-core
modules). The main technological
approach to stack these partitions
is wafer-to-wafer bonding – either
through hybrid (viamiddle) wafer-to-
wafer bonding or dielectric (via last)
wafer-to-wafer bonding techniques.
This is achieved by aligning top
and bottom wafers that are then
bonded. Recently, excellent results
in wafer-to-wafer overlay accuracy
have been obtained, for both hybrid
bonding (1.8 micrometer pitch) and
dielectric bonding (300nm overlay
across wafer). Accurate overlay is
needed to align the bonding pads of
the stacked wafers and it is essential
to achieving a high yield.
One of the main drivers for 3D-SOC
development is functional reparti-
tioning of high performance systems.
In such approach, different parts of
the SOC system are realized using
tailored technologies in different
physical layers, but remain tightly
interconnected.
The trend in processor development,
for example, has been towards an
ever increasing number of cores.
This trend will continue, enabled
by the scaling towards 7nm and
5nm technology nodes. More
cores will however also need more
on-chip memory. And all this will
result in more overall silicon area
and more back-end-of-line needs –
and hence, in an increasing wafer
cost. One way to cope with this
trend is by functional repartitioning
of the processor followed by
heterogeneous 3D integration.
New-Tech Magazine Europe l 47