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overall process which encompasses
everything of the SOC. For these
applications, partitioning in function
of scalability turns out an interesting
solution. If you split the technology
into parts that highly scale (e.g.
digital blocks) and parts that hardly
scale (e.g. analog blocks and I/O
drivers), you can optimize the die
with highly scalable technologies
separately from the die containing
less scalable technologies.
Further down the road:
3D-ICs
Eventually, the roadmap will lead to
even tighter integration, by stack-
ing transistors on top of each other,
achieving contact pitches as small
as (a few) 100nm. Imec explores
ways of stacking for example
nMOS transistors on top of pMOS
transistors – or vice versa – instead
of put-ting them next to each other
– also known as CFET (or CMOS
FET). This however involves a
completely different technology. It
is not about through-silicon-via-like
processes: it will be realized through
sequential processes or layer
transfer processes. The alignment
of the two transis-tors in a CFET
should not be wafer alignment
defined but lithography defined. A
Fig 6:
Imec’s 3D interconnect technology landscape.
Fig 7:
3D-die stack: four die,
connected vertically using 20
micrometer pitch microbumps
and 5 micrometer diameter, 50
micrometer deep TSV connections.
typical application is an SRAM cell
in a 3D format, which will have a
much smaller footprint than its 2D
equivalent. Another example is 3D
NAND technology, where a single
channel contains multiple tran-
sistors or bits (up to 58), integrated
into one single structure. So it is a
few levels of granularity lower than
3D-SOC partitioning. It is surely one
of the future paths with a potential
to extend Moore’s law scaling.
3D-SOCs and 3D-ICs complete
imec’s 3D technology roadmap
that out-lines different paths
for 3D integration. However,
imec researchers refer to a ‘3D
technology landscape’ instead of
a ‘roadmap’. It is not like a clear
traditional roadmap that can be
read from left to right. For 3D, there
are a lot of technology options that
will coexist, even within the same
system. The technologies differ in
where they intercept the hierarchy
of interconnects on the chip, in other
words, where we cut the devices
and make the 3D interconnectivity.
And this will determine the required
3D pitch. So it is more like a
collection of technologies that allow
a system to be integrated into a
much smaller form factor, with
increased performance and lower
manufacturing cost.
Dr. Mieke Van Bavel is science
editor at imec, reporting about
imec’s research and R&D results
in international magazines and
newsletters, and in imec’s public
magazine. Mieke has a PhD degree
in Physics (1995) from KU Leuven,
Belgium. Before joining imec, she
worked as a researcher in various
science institutes.
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